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(R)
STLC3040
SUBSCRIBER LINE INTERFACE CODEC FILTER, COFISLIC
Single chip CODEC and FILTER including all LOW-VOLTAGE SLIC functions. Advanced 12V BJT, 5V CMOS 0.8um technology. Low external component count. Over-sampling A/D and D/A conversion. No functional trimming or adjustments required. Serves a wide range of specifications; i.e. ITUT, LSSGR. A-law, and -law PCM and Linear voice coding, sw selectable GCI compatible interface. Programmable Digital-Filters for impedancematching, hybrid-balance, frequency-response and gain. Programmable Feeding-Resistance (2 x 50 to 2 x 400) and current-limiting (0-69.3mA). Programmable voltage-drop according to transmission needs. 12kHz/16kHz Teletax Generation with Programmable Level 0-10 Vrms in 40mV steps including shaping and filtering. Integrated Ring-Generator with Zero-Crossing. Programmable frequency from 16.6Hz to 60Hz, programmable level up to 85Vrms, Integrated auto ring-trip. Signalling functions ON/OFF - Hook, Gnd-key with filter and Programmable persistence check. Advanced test capabilities: On-board line tests and circuit tests. Signalling tests for meterpulse TTX and Ringing. Tone generator for circuit test. 3 Loop-back paths. Three operating conditions: Power Down, Active, Ringing. Off-hook programmable threshold-level in each of these conditions. Interface to High-Voltage SLIC to select modes, provide hard or soft Polarity-Reversal and sense HV (L3000N, L3000S, STLC3170) High Thermal condition. On-hook transmission capability. Selectable 2/4MHz backplane clock. Standard PLCC 44 package.
January 1999
PLCC44 ORDERING NUMBERS: STLC3040 STLC3040-TR
Figure 1: Pin Connection (Top view)
SEL24 DGND STR3
DCL
FSC
VDD
TS0
TS1
6 5 4 3 2 1 44 43 42 41 40 IO1 IO2 C1 C2 VL1 VL2 SIR0 CAP IL RAC SIR1 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
STR0 ACDC STR1 VBIM VOUT AGND PDO IT CAC RDC REF
D94TL161D
TS2
DU
DD
39 38 37 36 35 34 33 32 31 30 29
O1 I1 SIR2 MR IDH VCC VEE IDM IDL STR2 EXT
On chip Line-card identification. DESCRIPTION The subscriber line codec-filter, STLC3040, is fabricated in BiCMOS (12V bipolar / 5V CMOS) technology. It uses Digital-Signal-Processing(DSP) to implement central-office telephone interface features: DC-feed, Supervision, PCMCodec-Filter, Ring, Teletax metering (TTX) and Test functions. The STLC3040 is fully programmable and needs few external resistors and capacitors. The STLC3040 interfaces the subscriber's line via the High-Voltage (HV) (L3000N, L3000S, STLC3170) device and the central-office back1/49
STLC3040
DESCRIPTION (continued) plane via a GCI compatible interface (see fig.2). The GCI handles all STLC3040 control and voice channel. The STLC3040 processes the transversal linecurrent sensed by the ST HV (L3000N, L3000S, STLC3170) Line Driver Circuit and generates voltage-drive to the line via the HV (L3000N, L3000S, STLC3170), thus synthetizing the impedances required by various world administrations . Line impedances as well as the two-to-four wire conversion synthesis are software programmable. Also Transmit (Tx) and Receive(Rx) AC frequency-response, determined by DSP-filters, guarantee voice-band flat-response. Tx and Rx Gains are programmable as well. Digitized voice can be encoded on A-law or u-law. The DC characteristic is obtained by selecting limit-current value, DC-feed resistance (2 X 50 steps) and Drop-voltage. It also permits On-hook transmission and TTX pulse injection with filtering and shaping. TTX metering pulse generation (12 or 16kHz) has programmable amplitude up to 10 Vrms. Off-hook detection with programmable thresholds Figure 2: Functional Diagram.
LV STLC3040
FSC DCL DU DD A=-20 Iline IT ANALOG FRONT END HV CONTROL IL PDO C2 C1 IT IL REF C2 C1 VBIM CDVB CURRENT SENSORS GCI INT. DIGITAL SIGNAL PROCESSOR VOUT VIN A=20 RING RP2 TIP RP1 ITIP
is possible in all operating modes as described in section 4. Ring-signal with zero-crossing start/stop injection is generated on chip with programmable frequency and amplitude. In addition, when Ringtrip is detected, the Ring-signal is automatically disconnected at the next zero-crossing. Power consumption is kept low by providing a "Power-Down" mode where the HV-SLIC is switched off (Power Denial). A set of internal resistors connected to the line allows Off-hook detection in this mode. Overall power dissipation is around 50mW (max.) in Power Down mode. Several testing features are included in the STLC3040, both for self-test and to test line leakage, capacitance ..etc, thus saving on test equipment and relays. Measured DC quantities are digitized and sent via the B1 voice channel to the backplane. With proper software selection each signal can be modulated by a 1KHz carrier before being sent to B1 voice channel. Programmable linear code, software selectable, boosts the calculation resolution. Sigma-Delta converters (ASD: Analog, DSD: Digital) make the conversion independent of technology parameters (fig. 3).
HV L3000N
IRING
ACDC CAP RAC CAC RDC REF VCC
D95TL204B
STLC3040 PIN DESCRIPTION (This list is grouped according to Function)
N. Symbol Type (*) POWER SUPPLY 1 DGND PS Digital Ground 2 VDD PS +5V Digital Supply Voltage 27 AGND PS Analog Ground 33 VEE PS -5V Analog Supply Voltage 34 VCC PS +5V Analog Supply Voltage 2/49 Description
STLC3040
STLC3040 PIN DESCRIPTION (continued)
N. GCI 40 Symbol SEL24 Type (*) DI Description Select Clock Frequency for GCI Interface 2MHz/4MHz not affecting the data rate (2Mbit/s) If SEL24 = 0, Clock Frequency = 2048KHz If SEL24 = 1, Clock Frequency = 4096KHz GCI Select Time Slot Identifier Pins Frame Sync 8kHz GCI Interface Master Data Clock GCI Interface Data Down link GCI Interface Data Up link GCI Interface (Open Drain Driver) State Control Signal 1. Combination of C1 and C2 defines HV (L3000N, L3000S, STLC3170) operating mode. Current sense for thermal indication. State Control Signal 2. Combination of C1 and C2 defines HV (L3000N, L3000S, STLC3170) operating mode. Power down output. Proper bias current is provided to HV (L3000N, L3000S, STLC3170) by this pin. When the current is 0 the HV (L3000N, L3000S, STLC3170) goes in Power Denial (high impedance). Proper combinations of PDO with C1, C2 set additional operating modes for STLC3170 High Voltage Interface. Comparator Input. These are inputs of the comparator that senses the line voltage in Power Denial allowing Off/Hook detection in this mode. Longitudinal Line-Current input IL = (ITIP - IRING)/100. Transversal Line-Current input IT=(ITIP + IRING)/100. Battery image monitor. Output feeding the line voltage (DC, AC, RING, TTX) through H.V. HV (L3000N, L3000S, STLC3170).
43,42, TS0,TS1, DI 41 TS2 3 FSC DI 4 DCL DI 5 DD DI 6 DU OD INTERFACE TO HV SLIC 9 C1 AI/O 10 28 C2 PDO AO AO
11,12 15 19 25 26
VL1, VL2 IL IT VBIM VOUT
AI AI AI AI AO
I/O 7, 8 IO1, IO2 DI/O Programmable GCI controlled I/O. 39 O1 DO Digital output written via GCI. 38 I1 DI Digital input read via GCI. MISCELLANEOUS FUNCTION 29 EXT DI External Ring Sync. Input. 36 MR DI Master Reset Input. Active High. The STLC3040 is forced in Loop-open and internal registers are preset to default values. 31,32 IDL, IDM AI Identification Code Signals, M+L ternary digits 35 IDH DI H most significant bit, L least significant bit. 14 CAP AI/O Capacitor must be connected to this pin. Its value defines the Soft Battery Reversal slope. 16 RAC AI/O AC-Synthesis Reference Resistor. 20 ACDC AI/O AC/DC Line Split. Scaled line-current output, DC feedback input. 21 CAC AI Splitter Capacitor. Scaled AC line-current input. 22 RDC AI DC-Synthesis Reference Resistor. 23 REF AI/O Reference Voltage Output. A resistor on this pin sets the internal reference current. UNUSED 18,24 STR0,STR1 DI/O Reserved for testing, must be shorted to DGND. 30,44 STR2,STR3 13,17 SIR0, SIR1 DI/O Must be left open. 37 SIR2 DI/O Can be left open (*) Type AI AO AI/O Description Analog Input Analog Output Analog Input/Output Type DI PS DI/O Description Digital Input Chip Power/Ground Digital Input/Output Type DO OD Description Digital Output Open Drain Output
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STLC3040
4 FUNCTIONAL DESCRIPTION The STLC3040 is implemented by a combination of analog and digital circuits, merging the best available analog and digital processing performances of the BiCMOS technology. In particular two main blocks of the STLC3040 can be identified: an analog front end interfacing the HV (L3000N, L3000S, STLC3170) and a programmable DSP. (See fig. 3) 4.1 - Signal processing. The line-current signal received in pin IT from the HV (L3000N, L3000S, STLC3170) is mirrored out of pin ACDC. On its way, its value is sensed to determine Off-Hook signalling. While in active conversation this istantaneous sensing is used for fast Hook signalling such as numbering. Then line-current AC and DC parts are splitted by RDC and CAC. The signal is processed to realize AC and DC impedance synthesis. Indeed IT pin carries the AC current due to voice signals present at line terminals and the DC current related to the specific V-I operating point. During Stand-By mode signal is created by the DC current after AC part has been removed. This filtered Hook produces robust signalling in Standby mode or pause-period during reduced-power Ring mode. As far as the DC characteristic is concerned, two Figure 3: Block Diagram. different conditions are present and depend on loop resistance. a) Resistive Feed Region: the SLIC kit operates as a voltage source with a series resistance equal to (2Rp+n 2 50), where n can be programmed from 1 to 8 via CR8 register. Various values of voltage drops are possible as shown in Fig. 4. b) Constant current region: when IL reaches the programmed limiting current value (from 0 to 69.3mA; 1.1mA step via CR6 register), the Kit operates as a proper constant current source. (see Fig. 4). Concerning AC Processing the AC current-signal is converted to voltage on the reference resistor RAC (1620). Line impedance (real or complex) synthesis is carried out thanks to programmable filters. All the filters are integrated in the digital side of COFISLIC except the so called KA filter that is in the Analog Front End. KD and Z (in digital side) filters allow to match the line impedance if properly programmed. Furthermore KA ensures stability to impedance synthesis loop. In the Receive direction (Rx), the Analog Front End (AFE) receives a 1-bit modulated composite signal, which represents part of the voltage to be forced into the line. It performs DAC and filtering
DIGITAL SIGNAL PROCESSOR
A/u exp. LB1 Rx FSC DCL DU DD Tx GCI INT. Echo Canc. B GR R
ANALOG FRONT END
DSD LB3 Post Filter
+
TTX RING TEST Z
+
VOUT
LB1 GX
LB2
LB3 ASD
KA
D95TL205D
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+
Ilim
A/u Comp.
X
+
KD
DEC
ANTIALIAS FILTER
DC Char Curr. buff.
TTX Canc.
RDC
IT RDC
ACDC CAC
CAC
RAC
RAC
STLC3040
Figure 4.
IL ILIM RFEED = 2 * RP + n * 100 VDROP VBAT VOL IL 100mA (typ) RFEED = 2RP VL
VDROP = 9.6V + VdTTX .40 (see ILIM: 0-70mA 1.1mA step
par 4.3.2.1)
RING MODE
VBAT -22V IL ILIM RFEED = 2 * RP + n * 100
STAND-BY MODE ILIM: 0-70mA 1.1mA step
VL
VBAT -5.85V
D95TL208D
VL
functions. This voltage is then combined with the AC and DC analog impedance signals, plus a TTX pulse, in a summing buffer that feeds the Vin pin of the HV (L3000N, L3000S, STLC3170). The architecture of the digital section is based on Digital Signal Processor which synthetises 7 digital filters (B, Z, X, R, KD, GX, GR). KA uses the some register value as KD. In Table 1 you can find the number of coefficients and their bit width for each filter. Table 1:
FILTER B R X GR GX KA, KD Z NUMBER OF COEFFICIENTS 8 4 4 1 1 1 3 COEFFICIENT WIDTH 14 BITS 14 BITS 14 BITS 8 BITS 8 BITS 8, 14 BITS (*) 14 BITS
(*) KA is a subset of KD = most significant bits, (5-12) but sign bit, of KD register.
Filter coefficients can be programmed by 14 bits
deep registers. These internal filters can be enabled setting the most significant 5 bits of CR4 register and CR11 (1). PCM encoding and ITU-T high/lowpass-filtering are done by dedicated state machines. Setting the bit 0 of CR4 register A-law or -law can be selected. In order to match the complex line impedance, both amplitude and phase can be programmed using Filter Z. The two to four wires echo cancellation is implemented thanks to programmable echo canceler (B Filter) with Gain and Group-delay equalizer. Two programmable FIR filters X and R, can be set in order to guarantee the best overall line frequency response in the frequency domain, according to the local specifications. In this way the signal distorsion can be reduced with 14-bits resolution. Gain Setting, both in transmission and in receive, is done by two FIR filters (GX for transmission, GR for Receive). A coefficient optimization software let the users calculate GX and GR filters coefficients. In transmission the maximum achievable gain without distortion is 3dB.
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STLC3040
In receive the maximum programmable gain is 0dB. Gain step resolution in both sides (Rx and Tx) depends on the value of the gains. See table below to gain/step accuracy. Table 2.
Tx & Rx Gain Xmax - 6dB (1/128) Xmax - 12dB (1/64) Xmax - 18dB (1/32) Xmax - 24dB (1/16) Xmax - 30dB (1/8) Xmax - 36dB (1/4) Xmax - 42dB (1/2) Step accuracy 0.070dB 0.14dB 0.27dB 0.56dB 1.16dB 2.5dB 6.0dB pin 9 (C1) (*)Vmv (*)Vhv (*)Vhv Ext. Indication Ext. Indication pin (*)Vmv Ext. Indication 10 (C2) (*)Vlv Ext. Indication Ext. Indication Ext. Indication (*)Vlv Ext. Indication Ext. Indication Loop Open (HV Internal Resistors disconnect)
Table 3: PDO = 50A
pin 9 (C1) (*)Vhv (*)Vhv ST-BY CONV.NP CONV.RP (*)Vmv TIP OPEN BB.NP BB.RP (*)Vlv RING OPEN RING NP RING RP
pin 10 (C2) (*)Vmv (*)Vlv
PDO = 0A
Tx: Xmax = 3dB; Rx: Xmax = 0dB The Voice Signal Processing is shown in Block diagram in Fig.3. In the RX direction, after being decoded, the voice sample passes through a set of interpolator and correction filters. The signal is finally oversampled to a high-rate of 256kHz before being summed to the feed-back impedance synthesis signal. Analog circuits performs Off-Hook sense and allows On-Hook Signaling. The longitudinal line current provided by the HV (L3000N, L3000S, STLC3170) is sensed at pin IL; Ground Key signalling is activated when the absolute longitudinal current on IL pin exceeds threshold. A low pass filter and programmable persistance filter (register CR3) elaborates the detection. The Vbim pin receives from the HV (L3000N, L3000S, STLC3170) an information on the actual battery voltage (Vbim = Vbat/40), this voltage is then compared with the line voltage and one bit is set in the upstream data flow if Vline < (VOL/2). This allows the system to be tailored for different line requirements. Line and circuit-test functions are discussed in detail in the appendix. The HV (L3000N, L3000S, STLC3170) is driven by the STLC3040 through two ternary pins C1 and C2 (pin 9 & 10 of STLC3040) that define the operating state of the HV (L3000N, L3000S, STLC3170) (Table 3). C1 and C2 are set according to the content of the bytes received by STLC3040 at DD pin (pin 5) of the GCI Interface. C1 pin is internally tied to a current-sensing circuit. It senses an extra current that the HV (L3000N, L3000S, STLC3170) issues when in thermal overload conditions.
(*) Vhv, Vmv, Vlv see digital interface electrical characteristics.
Through PDO pin (pin 28) the STLC3040 forces the HV (L3000N, L3000S, STLC3170) in Power Denial if the current at this pin is 0. When the STLC3040 sinks 50A the HV (L3000N, L3000S, STLC3170) will be turned on. In Power Denial, TIP and RING wires are disconnected from the HV (L3000N, L3000S, STLC3170) driver (Power Denial). Table 3 related to PDO = 0A is valid only for STLC3170. VL1, VL2 pins sense, the Off-Hook when HV (L3000N, L3000S, STLC3170) is in power denial, allowing very low power consumption in On-Hook condition. Other important features, which usually require external circuitry, like Test Tones, Ringing, Metering Impulse Injection are programmable via software. Ring signals can be programmed both in Amplitude and Frequency via CR9 register. The Metering Pulse Injection Level can be set by the CR10 register. Ring-Trip detection is performed by a dedicated internal circuitry. 4.3 Slic Kit Operating Modes STLC3040/HV (L3000N, L3000S, STLC3170) kit can work in three main modes: - POWER DOWN - ACTIVE - RING Each mode is selected by Command-Indicate (C/I) and Monitor GCI channels. Line State changes are signalled through either upstream C/I or SR register. During the switching between any two modes the indication is frozen for 10msec in addition to the programmed persis-
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STLC3040
tance. All operating modes with related C/I command bits and CR register bits are shown in table 13 pag 45. 4.3.1 POWER DOWN In this condition SLIC Kit reduces strongly its power consumption allowing Off-Hook detection. Only the internal circuitry dedicated to the OffHook detection is switched on. C/I and CR1 register configuration (programmed by Monitor) defining Power Down Submodes are here below shown: Table 4: Power Down Submodes
SLIC KIT MODE EXTERNAL INDICATION LOOP OPEN STAND BY GROUND START C/I (7) 0 0 0 0 C/I (6) 0 0 0 0 C/I (5) 0 1 0 0 CR1 CR1 CR1 (7) (3) (2) 0 X 1 1 X X 0 1 X X 0 1
RING pins; theHV shows on TIP pin the RT impedance and on RING pin the RR impedance if it integrates the 2 external resistors RT and RR (STLC3170). This mode is used to get a low power consumption obtaining supervision only via the STLC3040 and a resistive sensing network. The total power consumption of the SLIC Kit in this mode is under to 50mW (being almost 0 the consumption from battery). 4.3.1.2 - Loop Open This mode can be selected only if the High Voltage integrates the two external resistors (RR, RT see fig. 5) of the feeding and sensing circuitry. This is implemented on the STLC3170 high voltage device. 4.3.1.3 - Stand-By SLIC behaves like a constant current source with typical 7mA feeding current. Open loop voltage is equal to (Vbat - 5.85V). COFISLIC power consumption is reduced to 150mW typical. Current limit and Off-Hook threshold are programmable by register CR7. Both off-hook and ground-key detectors are operating. 4.3.1.4 - Ground Start The SLIC is set in Stand-By with the TIP wire (the most positive wire) in high impedance. The current feeding is equal to Stand-By mode current feeding.
4.3.1.1 - External Indication When this mode is selected both STLC3040 and HV (L3000N, L3000S, STLC3170) are set in Power Denial. STLC3040 cuts the bias current, sunk by the HV (L3000N, L3000S, STLC3170) via the PDO pin. In this mode the HV (L3000N, L3000S) shows a high impedance on TIP and Figure 5: Application Diagram.
BGND AGND
VCC
VB+
VCC
VDD
VEE
AGND DGND
RT RP TIP
VIN REF IT MNT IL
VOUT PDO IT IL C1 C2 VBIM CDVB
EXT SEL24 DU/DD(2) DCL FSC TSn(3)
RP
RING RR
L3000S
Power SO20
C1 C2 VBIM
STLC3040
44PLCC
IOn(2) O1 I1 MR IDn(3) STRn/SIRn(7)
DS VBBGND
VL2 VL1 REF REF RAC RAC RDC RDC ACDC
CAP
CAC CAC CAP
D95TL203B
VCC
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STLC3040
4.3.2 - ACTIVE This operating mode is selected by the card processor after an Off-Hook detection in order to allow signal transmission on the line. Both Off-Hook and ground-key detectors are operating. GCI Command - Indicate channel and CR1 register configuration (programmed by GCI Monitor) defining Active modes are herebelow shown: Table 5:
SLIC MODE ACTIVE ACTIVE + TTX C/I (7) 0 0 C/I (6) 1 1 C/I (5) 0 1 CR1 (*)CR1 (*)CR1 (7) (3) (2) X X 1/0 1/0 1/0 1/0
(*) This condition refers to STLC3040 only. If CR1.3 and CR1.2 are equal (either 0 or 1) both STLC3040 and HV (L3000N, L3000S, STLC3170) are in Active State. If CR1.3 and CR1.2 are different, one of two line wires will be set in high impedance, while the STLC3040 will still be in Active mode.
Current Limit and Off-Hook threshold are programmable by CR6 register. If the fifth bit of the Command-Indicate channel is set to 1 the Teletax Signal is superimposed to the voice signal. 4.3.2.1 - DC feeding As far as DC characteristic is concerned, SLIC is basically working as a constant current device. It turns automatically into a resistive feeding when the programmed current limitation value cannot be held due to high line resistance. In active mode the constant current value is programmable Figure 6: TTX Shaping
in 1.1mA steps ranging from 0mA to 69.3mA. In resistive feeding region SLIC kit operates like a constant voltage source with a series impedance Rfeed = 2Rp+n 2 50 (being Rp the external protection resistor and n a value set from 1 to 8 via CR8 register). Voltage drop (Fig. 4) can be programmed in order to optimize voltage feeding characteristic, according to AC signal swing requested (ex: voice, voice + 2Vrms TTX, voice + 5Vrms TTX): VDROP = Vd3000 + 40 (VdAC + VdTTX) Vd3000 = drop due to internal HV (L3000N, L3000S, STLC3170) architecture (2.8V typ.) VdAC = AC headroom on Vout (170mV typ.) VdTTX = TTX headroom on Vout (from 0 to 465mV (15x31) typ. depending on programmed TTX level). At HV (L3000N, L3000S, STLC3170) two wires the following equation must be used: VDROP(TIP/RING) = 9.6V + CR10 [7..3] 15mV 40. 4.3.2.2 - Metering Generation TTX signal is internally generated, filtered and shaped. Shaping is carried out by a gradual increase of metering pulse level of a level step (see CR10 register) per signal half period (please see Fig. 6). TTX can be programmed both in frequency (12 or 16 KHz ) and open loop amplitude (from 0 to 10Vrms in 255 steps). The output impedance at TTX frequency is just 2 x Rp; therefore the proper value should consider the drops
VS
VSS
TIM
D96TL265A
VS 2 CR10 LSB VSS PROGRAMMED VOLTAGE AS PROG IN CR10
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STLC3040
across the 2Rp. Filtering is performed inside the device without external circuitry. Feeding voltage polarity can be reversed in both soft and hard ways under software command. 4.3.2.3 - Boost Battery To supply very long lines (high loop resistance), the SLIC can be set in "Boost battery" mode. In this mode the line is fed with a total battery voltage equal to |Vb+| + |Vb-|, keeping the same current limiting values as in active mode. The Vb+ battery is the same positive supply voltage needed for ringing generation. 4.3.3 - RING In this mode COFISLIC provides ringing signal equivalent to a maximum 85Vrms ring line voltage. HV L3000N and L3000S handle a maximum 65Vrms balanced ring signal; HV STLC3170 handles a maximum 85Vrms. It is possible to reduce power consumption if Power Reduced Ring mode is chosen. The output impedance is represented only by the two Rp protection resistors and the current is limited to 100mA. C/I and CR1 register configuration (programmed by GCI monitor channel) define Ring conditions as herebelow shown: Table 6:
SLIC MODE RING Reduced Power Ring C/I (7) 1 1 C/I (6) 1 0 C/I (5) X X CR1 CR1(*) CR1(*) (7) (3) (2) X 1/0 1/0 X 1/0 1/0
sent to C/I upstream. 4.3.3.2 - Power Reduced Ring The modes in Table 6 differ only during the ringpause phase. During the pause of reduced-power-ring mode the SLIC Kit is set in Stand-By. The pause state is forced by stop ring command (C/I.5 downstream = 0) or by the detection of OffHook. 4.3.3.3 - Unbalanced Ringing The device allows an unbalanced Ring application. This application requires an external ringing generator. A digital I/O pin can be used to drive the external relay driver. An external ring sync. signal synchronised on the Vring zero crossing, must be provided on pin 29 of STLC3040. The external ring frequency must be the same as the value programmed in the internal register. 4.4 - TESTING FEATURES STLC3040/HV (L3000N, L3000S, STLC3170) kit allows to perform up to 11 tests. They are aimed at covering the following issues. 1. Line and Battery Characteristics AC, DC Leakage. 2. SLIC Kit block testing. 3. Signal Path Behavior Every test is set by internal registers, which are written through GCI data down Monitor. Test results are typically digitalized, codified and dropped in the first PCM channel (byte B1) of GCI interface. For four go/nogo tests (Analog Loopback, Ring Generator, TTX Generator and TTX filter) the result of the test is also written in one bit of CR5 register that is readable through Monitor. Test functions are carried out with SLIC Kit in a mode set automatically by COFISLIC. For detailed explanation about tests see chapter 6. 4.4.2 - Loop Backs LOOP1 and LOOP2 bits of CR4 register set up some internal loop backs. This feature is typically used for COFISLIC tests (see fig. 3). Any Loopback is enabled by CR1.5 bit. Loopback type is selected by register CR4. There are three types of loopback. Loopback 1 (CR4.2 = 0, CR4.1 = 1) simply copies the downstream B1 to the upstream B1 through the GCI interface. In this case no Rx signal is sent to the line. The kit operates as previously set. Loopback 2 (CR4.2 = 1, CR4.1 = 0) sets Kit SLIC in Active mode. It copies the output of DSD (Digital Sigma Delta converter) to the input of the DEC
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(*) CR1.3 has to be equal to CR1.2 : 0 or 1
If unbalanced ringing is requested, SLIC can support also external ringing injection configuration, providing both logic command for relay driver and ringing detection circuitry. 4.3.3.1 - Ring Generation When the ringing function is selected, a low level ringing signal (1.5Vrms typ.) is generated inside the STLC3040 and provided on the VOUT pin. This signal is then amplified and injected in balanced mode into the line through the HV (L3000N, L3000S, STLC3170), with superimposed DC voltage of 24V typical. Both ringing frequency and amplitude are software programmable. The first and the last ring cycles are synchronized by the STLC3040 so that the ringing signal always starts and stops with zero phase. In Ring mode the Off Hook indication is asserted whenever during two consecutive ring periods ( or an equivalent time in pause) the mean value of the IT current exceedes the programmed threshold. After the persistance time the Off Hook is
STLC3040
block, as shown in fig. 3. Rx signal goes on to the line. Please note that this loopback function cuts off the Tx channel connection to the line. All other functionalities are those of Active mode. Loopback 3 (CR4.2 = 1, CR4.1 = 1) sets Kit SLIC in Active mode. Rx signal is prevented to go the line. Tx path is cut off from the line as well. Output of ASD is copied to input of AFE port filter. DSP part can be still exercised via B1. All the functionalities are those of active mode. 4.4.3 - Test Tones Generation In Active mode STL3040 can generate either 1kHz or 800Hz frequencies towards the 2-wire line. The two tones can also be enabled at the same time. TON bit of CR1 register enables the 1 kHz test tone generator. 800Hz is enabled by CR5[3.0] = 4h. 800Hz amplitude is programmable through the same register (CR10) used to set TTX amplitude. 1kHz level is fixed at PCM full scale and can be modified changing Rx channel gain. 4.5 COFISLIC Reset Any reset to COFISLIC sets SLIC kit in External Indication. COFISLIC is set in Power denial. There are four different reset sources: Power-On Reset, Reset pin MR (pin 36), Reset bit (SOP command bit 4). During Reset, output pins are set as follows:
DU C1 C2 PDO O1 (pin 6) (pin 9) (pin 10) (pin 28) ( pin 39) High impedance Vhv Vhv High impedance Low Level
4.5.1.3 Reset bit RST (SOP command bit 4) If RST bit is programmed to 1 COFISLIC is reset. SOP register is set by GCI down stream channel. Until the end of the current command processing, the GCI is kept active. 4.5.1.4 - CLK fail Reset Clock fail triggers a reset routine of the DSP which lasts, until the first good frame that follows the failed ones. In active mode during the Reset routine, the voice channel of "Data up" (Du, pin 6) is forced IDLE dependent on the selected codification law. As far as "Data down" (DD, pin 5) is concerned, the voice channel does not reach the Vout during this phase. Z sinthesys is partially performed, the DSP branch is not active while the analog loop is kept active. Coefficients and CR registers' contents do not change because of this partial reset, GCI state as well. Metering pulse injection signaling is not affected too. Ring generation and ring trip detection are not influenced too. 4.5.2. Start-up State During reset the device is in Power- Denial Mode. After Reset, COFISLIC is automatically switched to its basic start-up state in which it uses internal default values for all filters and settings (AC and DC). Programmed coefficients of filters are not reset. Bit 0 of CR6 register, FIXC, is set to 1, this means that fixed values are used after a Reset until FIXC is set to 0. Even if FIXC = 1, both checksum and reading of filter coefficients are carried out on formerly programmed coefficient set. Table 7: Fixed Filter Coefficients
Filter KA, KD Z X R GTX GRX B Coefficients (h) 0E00 019C, 24A0, 1600 149A, 0521, 3F40,3EF2 1879, 39E0, 00B4,0006 FF 60 0, 0, 0, 0050, 0680, 06D0, 0, 3C80
Additionally a Reset of the DSP part of the COFISLIC is triggered by CLK fail detection (see also page 17). 4.5.1.1 Power On Reset When voltage at VDD pin crosses over an internal fixed threshold (typ. 2.5V) COFISLIC is reset. 4.5.1.2 Reset Pin MR If an high level is applied to pin 36 (MR) the COFISLIC is reset. MR pin has built-in filter to reduce spike sensitivity. Spikes smaller than 90ns are neglected. Therefore at MR pin a high level is surely recognised as a Reset if it is present for at least 2s.
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SLIC is switched to operating mode carried by GCI Command Indicate at least two frames after reset. SLIC status and Filter configuration can be changed by SOP and COP commands. After reset the device is internally set as follows: - configuration registers are set to their default
STLC3040
values (see Chapter 4-8 Configuration Register) - RST bit (SOP command bit 4) is set to 1 to indicate that a reset has occured - GCI interface is reset. After software Reset its former state is kept. On-going GCI communication is stopped - DU is in high impedance state - FIXC = 1 (CR6 Register) Fixed Coefficients are selected - DC characteristics of SLIC-Kit - External Indication - Normal Battery - Test Disabled - Persistence for Off-Hook and I1: 10ms - Persistence for Ground Key: 20ms - Ring Trip threshold = 4.2mA - Ilim = 22mA in active mode - Ilim = 7.7mA in Stand-By mode - Off-Hook detection threshold in active mode = 10mA - Off-Hook detection threshold in Stand-By mode = 7.7mA - Feeding Resistance in either Active or StandBy mode = 2 (50 + Rp) (fuse impedance value is not included) - Ring: Internal - Ring Frequency = 25Hz - Ring Voltage = 65Vrms - Line Voltage Drop = 28.2V - External Indication Voltage Threshold for OffHook detection = 9.0V - A-law is programmed AC characteristics of SLIC-Kit - Metering with Teletax - Line Impedance: (Synthetized Impedance + 2 Rp) = 700 + 2Rp - Balance Impedance: 910 / / 62nF - Tx Gain: 0dBr - Rx Gain: -7dBr - Teletax Voltage onto line VTTX = 10Vrms - Teletax Frequency = 16kHz - Battery Reversal: Hard Further after the reset - I/O pins are set as inputs - PD bit of CR1 is reset (means STLC3040 in Power-Denial mode). - All bits of Signalling Register are masked - Data Upstream C/I byte is reset to 0 Check Configuration-registers more detailed information. reset-value for
4.6 GCI Backplane Interface GCI is a standard serial interface for interconnection of SLIC kit to the line card backplane. The digital interface is used to transfer status information to and from the SLIC as well as to transfer filter coefficients for the DSP. With this approach an analog Line Card could be replaced by an ISDN one and viceversa without need to change the interface to the linecard controller. As far as physical level is concerned this standard consists of four wires: - Serial Transmitted data to the backplane: DU - Serial Received data from the backplane: DD - 8KHz Frame Synchronization: FSC - Master Data Clock (2048KHz or 4096KHz): DCL The frame is divided into eight time-slots which contains four bytes each. Bit rate in both directions is 2048Kbit/sec and it's not affected by clock frequency. This can be chosen setting SEL24 pin. Eight GCI time slots are selectable via three pins TS2-TS0 (see Table 8). For every time slot the first bit, received or transmitted, is the Most Significant one, according to timing diagram shown in fig. 7. Information is clocked out on the rising edge of data clock and it is latched in on the falling edge of DCL signal. Frame Synchronization FSC is a 8KHz signal and its rising edge gives the time reference of the first bit in the first GCI (input or output) channel and resets the slot counter at the next falling edge of the clock every frame. Four bytes of any GCI time slot are: - B1 channel for PCM data, - B2 channel not used, - M (Monitor) channel used to write and monitor COFISLIC internal registers, - C/I (Command/Indication) channel used to set the Operating Mode.
8bits B1 Byte 1 8bits B2 Byte 2 8bits MONITOR Byte 3 6bits C/I 1bit A Byte 4 1bit E
A single GCI channel has 256kbit/s data rate. Exchange Protocol STLC3040 validates a received byte if it is detected identical two consecutive times. (see figg. and 7and 8) The exchange protocol is identical for both directions. The sender uses the E bit to indicate that it is sending a Monitor byte while the receiver uses A bit to acknowledge the received byte. When no
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STLC3040
Table 8: GCI Time Slot assignment.
SEL24 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 GCI operating mode time slot 0:DCL = 2048kHz time slot 1:DCL = 2048kHz time slot 2:DCL = 2048kHz time slot 3:DCL = 2048kHz time slot 4:DCL = 2048kHz time slot 5:DCL = 2048kHz time slot 6:DCL = 2048kHz time slot 7:DCL = 2048kHz time slot 0:DCL = 4096kHz time slot 1:DCL = 4096kHz time slot 2:DCL = 4096kHz time slot 3:DCL = 4096kHz time slot 4:DCL = 4096kHz time slot 5:DCL = 4096kHz time slot 6:DCL = 4096kHz time slot 7:DCL = 4096kHz
Figure 7.
GCI Interface Timing (DCL = 2048KHz, SEL24 = 0)
125s
FSC DCL
2048KHz TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
DD DU
TS0 Detail C
TS1
TS2
TS3
TS4
TS5
TS6
TS7
Detail C FSC DCL DD/DU
Bit 0 Bit n Bitn - 1
D95TL210A
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STLC3040
Figure 7. (continued)
GCI Interface Timing for 8 voice channels (per 8 KHz frame)
125s
FSC DCL
4096KHz TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
DD DU
TS0
TS1
TS2 Detail A
TS3
TS4
TS5
TS6
TS7
Detail A DD DU
Voice Channel don't care Monitor Channel C/I Channel A E
Voice Channel
High Impedance
Monitor Channel
C/I Channel A E
GCI Interface Timing (DCL = 4096KHz, SEL24 = 1, per 8 KHz frame)
125s
FSC DCL
4096KHz TS0 TS1 TS2 TS3 TS4 TS5 TS6 TS7
DD DU
TS0 Detail B
TS1
TS2
TS3
TS4
TS5
TS6
TS7
Detail B FSC DCL DD/DU
Bit 0 Bit n Bit n-1
D95TL209A
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STLC3040
message is transferred, E bit and A bit are forced to inactive state (high = 5V). A transmission is started by the sender (Transmit section of the Monitor channel protocol handler) by putting the E bit from inactive to active state (low = 0V) and by sending the first byte on Monitor channel in the same frame. Transmission of a message is allowed only if A bit, sent from the receiver, has been set inactive for at least one consecutive frame. When the receiver is ready, it validates the incoming byte when received identical in two consecutive frames. Then, the receiver sets A bit from the inactive to the active state (preacknowledgement) and maintain active at least in the following frame (acknowledgement). If validation is not possible (two last bytes received are not identical) the receiver aborts the message by setting the A bit active for only a single frame.The second byte can be transmitted by the sender putting the E bit from the active to the inactive state and sending the second byte on the Monitor channel in the same frame . The E bit is set inactive for only one frame. If it remains inactive more than one frame, it means an end of message. The second byte may be transmitted only after receiving of the pre-acknowledgement of the previous byte . Each byte has to be transmitted at least in two consecutive frames. The receiver validates the current received byte as for the first one and then set the A bit in the next two frames first from the active state to the inactive state (pre-acknowledgement) and back to the active (acknowledgement). If the receiver cannot validate the received current byte (two bytes received not identical)it pre-acknowledges normally but lets the A bit in the inactive state in the next frame which indicates an abort request . If a message sent by the COFISLIC is aborted, the COFISLIC will send again the complete message until receiving of an acknowledgement . A message received by the COFISLIC can be acknowledged or aborted with flow Control. The most significant bit (MSB) of Monitor byte is sent first on the Monitor channel. E & A bits are active low and inactive state on DU is 5 V. When no byte is transmitted, Monitor channel time slot on DU is in the high impedance state. The GCI interface transmitter will abort after 8 times during which it hasn't succesfully received any acknowledge from the device upstream. The GCI interface receiver will go in abort request mode after 8 times of unsuccessful attempts to get 2 identical copies of the data. This means that after 8 frames of unsuccessful handshake, the GCI interface transmitter will abort while the receiver will make a request for abort. 4.6.1 B1/B2 Channels 4.6.1.1 PCM codifications GCI interface extracts receiving PCM data from
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the B1 channel on DD pin and outputs PCM bytes on DU pin. 4.6.1.2 Linear codification STLC3040 allows Linear codification simply setting two bits of CR12 register. COMTX (bit 0) enables the linear code in transmission, while COMRX (bit 1) enables the linear code in receive. STLC3040's linear code consists of 16 bits which means a range from (-215) to (215-1) Linear Code is housed in B1 and B2 channels, B1 is the least significant byte end B2 is the most significant byte. 15 bits are dedicated to the module while the most significant bit is the sign bit. If bit 15 (sign bit) = 0 bit 14.....bit 0 represent the module. If bit 15 = 1 module is got by 2-complementing bit 14 ...... bit 0. 4.6.2 C/I Channel Command/Indicate byte is a 6 bits wide command full duplex transmission. Internal C/I registers will be loaded if downstream command is stable for two frames. Also upstream Command/Indicate byte lasts for at least two consecutive 8KHz frames. Command/Indicate is mainly used to set SLIC operating mode and to monitor subscriber On/Off-Hook and Ground-Key detection. Any change of line conditions like On-Off/Hook and Ground Key is signalled via upstream C/I. HOOK and GNDK bits always reflect line conditions even if corresponding bits of Signalling Register are masked by CR12 register. Bit 5 of upstream Command/Indicate says that at least one of Signalling Register six most significant bits has changed its logical value. Bit 5 of upstream Command/Indicate does not change if related bits of Signalling Register have been masked by CR12 register. Input/Output pins (IO1/2,I1,O1) can be set and monitored by C/I channel too. Note that there is no address in both directions because there is one GCI time slot per each COFISLIC. C/I channel in Downstream direction consists of six bits as shown below :
BIT7 RING BIT6 CONV BIT5 TIM BIT4 IO1 BIT3 IO2 BIT2 O1
Basically the first 3 Most significant Bits of C/I downstrean operate as follows. For a complete description please refer to Table 13.
STLC3040
Figure 8: GCI Monitor Channel messaging examples.
M E A
X
M1
M1
M2
M2
X
X
X
1st byte (M1) Ready for a message pre-ack (M1) ack (M1)
2nd byte (M2) pre-ack (M2) ack (M2)
3rd byte?? (X)
EOM pre-ack?? (X)
Ready for a new message
TWO BYTES MESSAGE - NORMAL TRANSMISSION
X
M1
M1
M2
M2
X
X
X
M E A
X
M1
M1
M2
1st byte (M1) Ready for a message pre-ack (M1)
2nd byte (M2) ack (M1) pre-ack (M2)
3rd byte?? (X) abort (M2)
EOM (or abort ack) Ready for retransmission
1st byte (M1)
pre-ack (M1)
TWO BYTES MESSAGE ABORTED ON THE SECOND AND RETRANSMITTED
M1 = start Byte
E & A BITS TIMING
RING = Sets COFISLIC into ringing state. = 0 COFISLIC is not in ringing state. = 1 COFISLIC is in ringing state. CONV = Sets COFISLIC into power up state. = 0 COFISLIC is in a power down state. = 1 COFISLIC in power up state. TIM = Timing bit to control the timing of ringing and meterpulses. = 0 COFISLIC is in ringing pause or no meterpulse is on. = 1 COFISLIC is in ringing or output of a meterpulse is running.
IO1, IO2 define the value for the programmable Input/Output pins (7, 8) if programmed as output pins by CR2 register. IO1 = 0 The related pin 7 at the digital interface of the COFISLIC is set to a logic 0 = 1 The related pin 7 at the digital interface of the COFISLIC is set to a logic 1 IO2 = 0 The related pin 8 at the digital interface of the COFISLIC is set to a logic 0 = 1 The related pin 8 at the digital interface of the COFISLIC is set to a logic 1 O1 sets value for fixed output pin 39
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STLC3040
= 0 The related pin 39 at the digital interface of the COFISLIC is set to a logic 0 = 1 The related pin 39 at the digital interface of the COFISLIC is set to a logic 1 C/I channel in Upstream direction is herebelow described:
BIT7 HOOK BIT6 GNDK BIT5 SLCX BIT4 IO1 BIT3 IO2 BIT2 I1
channel transfers: SOP, COP, TOP.
BIT7 X R/W B3 0 1 X BIT6 R/W =0 =1 B2 1 1 0 SOP command TOP command COP command BIT5 X BIT4 X BIT3 B3 BIT2 B2 BIT1 X BIT0 X
Write Operation Read Operation
HOOK indicates loop condition: = 0 Subscriber is On-Hook = 1 Subscriber is Off-Hook GNDK indicates Ground Key detection: = 0 No Detected Longitudinal Current = 1 Detected Longitudinal Current SLCX is the summary output of the signalling register (See TOP command) = 0 No unmasked bit in signalling register has toggled = 1 An unmasked bit in signalling register, has toggled, it is reset only if SR register is read. IO1,IO2 give logical state of programmable Input/Output pins (7, 8) IO1 = 0 Corresponding pin 7 at digital interface of COFISLIC is receiving a logic 0 = 1 Corresponding pin 7 at digital interface of COFISLIC is receiving a logic 1 IO2 = 0 Corresponding pin 8 at digital interface of the COFISLIC is receiving a logic 0 = 1 Corresponding pin 8 at digital interface of COFISLIC is receiving a logic 1 If as per CR1 register IO1 and IO2 are programmed as outputs, data up command indicate, IO1 and IO2 are set to 1 I1 gives logical state of fixed input pin 38. = 0 pin 38 is receiving a logic 0. = 1 pin 38 is receiving a logic 1. 4.7.1 Monitor-Channel (M-channel) As already mentioned COFISLIC can be programmed and monitored via GCI Monitor. Data transfer from and to STLC3040 starts with a specific byte, called Start Byte:
BIT7 1 BIT6 0 BIT5 0 BIT4 0 BIT3 0 BIT2 0 BIT1 0 BIT0 X
For SOP, COP, TOP commands the Start Byte is 81 in DU directions. SOP commands set and monitor COFISLIC status. TOP commands read Signalling register and coefficient checksum. COP commands set and read filters coefficient. SOP and COP can be either write or read commands, while TOP is used only for reading. A write command (SOP and COP) can be followed by up to 14 bytes. An answer to SOP, COP, TOP commands consists of maximum 16 bytes. First byte is always the start byte (81h). Registers from CR1 to CR12 are accessed by SOP command both in reading and writing. TOP command is used to read the Signalling Register and the Coefficient Checksum. The RAM, where filters coefficient are stored, is accessed by COP commands. A fourth command of the Monitor Channel is the so called Channel Identification Command (CIC). This command will be run if the COFISLIC receives the following code on the Monitor Channel for at least two frames:
BIT7 1 BIT6 0 BIT5 0 BIT4 0 BIT3 0 BIT2 0 BIT1 0 BIT0 0
Upon CIC command is received COFISLIC will place two bytes on DU line, each byte is repeated at least twice.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 1 0 0 0 CONF(3) CONF(2) CONF(1) CONF(0)
This byte replaces usual Start byte. Low nibble CONF(3)-CONF(0) defines the identification code according to the logic values of three input pins IDH (pin 35), IDL and IDM (pin 31 and 32). Herebelow it is the Table of Identification:
In downstream a second byte selects one of the three different kinds of commands which Monitor
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STLC3040
Table 9:
IDH +5V +5V +5V +5V +5V +5V +5V +5V 0V 0V 0V 0V 0V 0V 0V 0V IDM -5V -5V -5V 0V 0V 0V +5V +5V +5V +5V 0V 0V 0V -5V -5V -5V IDL -5V 0V +5V -5V 0V +5V -5V 0V 0V -5V +5V 0V -5V +5V 0V -5V Id. Code 0 1 2 3 4 5 6 7 8 9 A B C D E F BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 XX XX
HOOK GNDK VB_2 ILIM TEMP CK_FAIL
SIGNALLING REGISTER (SR) SR provides information about loop condition: Off/OnHook condition, line constant current, line voltage. It also signals temperature alarm related to HV SLIC (L3000N, L3000S, STLC3170) and clock fails (see page 10). The Clock fail indication is set whenever the number of DCL periods in one frame (between two-FSC pulses) is different from the standard one. Hook and Ground Key state variations toggle the related bits of SR register and therefore switch HOOK and GNDK bits of upstream C/I. Every change of any of the six most significative bits of SR register is summarized in SLCX bit (bit 5) of upstream Command/Indicate, provided that these bits are not masked by CR12 register. Masking acts only on SLCX bit.
Reset Value: 00h HOOK indicates loop condition (same as in upstream C/I): = 0 Subscriber is On-Hook = 1 Subscriber is Off-Hook GNDK shows a Ground Key detection (same as in upstream C/I): = 0 No Detected Longitudinal Current = 1 Detected Longitudinal Current VB_2 half battery voltage across the line is detected VOL ). (VLINE compared to 2 This bit is designed to indicate the line DC operating point only in Stand-By and Active modes, with no TTX injection = 0 if (|VLINE|<| VOL |) 2 VOL = 1 if (|VLINE|>| |) 2
Data transfer is completed by the next byte:
BIT7 1 BIT6 0 BIT5 0 BIT4 0 BIT3 1 BIT2 0 BIT1 0 BIT0 0
4.7.1.1 TOP Command As above mentioned TOP command allows reading Signalling Register and Coefficient RAM checksum.
BIT7 X BIT6 R/W BIT5 X BIT4 X BIT3 1 BIT2 1 BIT1 BIT0 LSEL1 LSEL0
R/W = 0 No Operation = 1 Read Operation
LSEL1 0 0 LSEL0 0 1 1 byte for signalling register reading 1 byte for signalling register and 2 bytes for filter coefficients checksum reading, low byte is read first and then high byte. 15 bytes for Line Card Identification Code reading
1
0
In answer to TOP command COFISLIC will place the Start byte first. Coefficient checksum is defined by this algorithm: X16 X10 X7 X 1 This algorithm guarantees a fault coverage of: (1 - 2-15)
where: |VLINE| = |VTIP - VRING| |VOL| = |VBAT-VDROP| ILIM Current Limit Region This interrupt is automatically masked in Ringing Mode = 0 Resistive Feeding Region = 1 Constant Current Feeding Region TEMP Temperature alarm of HV SLIC (L3000N, L3000S, STLC3170) which is signalled through HV (L3000N, L3000S, STLC3170) interface = 0 Normal Temperature
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= 1 Temperature Alarm from HV (L3000N, L3000S, STLC3170) CK_FAIL Receiving Clock and/or Synchronization signals failures = 0 no Detected Clock or Sync fails = 1 Detected Clock or Sync fails Bits ILIM, TEMP, VB_2 have 7ms persistance fixed. 4.7.1.2 COP Command Every COP command is started by the Start Address. A second byte contains the RAM address related to the programmable filters. Address is defined by the least significative five bits except the third one which identifies a COP command. COP commands consist of maximum 14 bytes used to set and monitor digital filter coefficients. COP register:
BIT7 X BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 R/W COD5 COD4 COD3 COD2 COD1 COD0
command the SOP is started by Start Byte, in downstream, followed by a byte that sets the SOP register. SOP register:
BIT7 X BIT6 R/W BIT5 POL BIT4 RST BIT3 0 BIT2 1 BIT1 BIT0 LSEL1 LSEL0
R/W = 0 Write to Cofislic = 1 Read Operation POL = 0 Normal Polarity Feeding = 1 Reverse Polarity Feeding RST = 0 Normal Operation = 1 Reset, set the COFISLIC to the basic setting mode After a reset, RST is set to 1. RST is toggled to 0 after a SOP read operation with LSEL bits programmed to 00b.
If R/W = 0 LSEL1 LSEL0 0 0 1 1 0 1 0 1 Write to COFISLIC No byte is following Two bytes, which write CR1 and CR2 Registers, follow 12 bytes, which set CR1,.,CR12 registers, follow Not available Read from COFISLIC Replies the SOP * command received by COFISLIC Replies the SOP * command received by COFISLIC, followed by two bytes: CR1, CR2 Registers Replies the SOP * command received by COFISLIC, followed by twelve bytes: CR1, CR2 CR12 Registers Not available
R/W = 0 Subsequent bytes are written to COFISLIC = 1 Subsequent bytes are read from COFISLIC COD2 = 0 Identifies a COP command COD5, COD4, COD3, COD1, COD0 bits identify filters address as shown here below (Table 10). For every coefficient, but B filter, with 14bit width the Least significant Byte is sent first. In the Most Significant Byte the first two bits must be stuffed with 0. For B Filter the 14 bytes are the result of the concatenation of the 8 coefficients of 14 bits 4.7.1.3 SOP Command Reading and writing of CR and SOP register is performed via SOP commands. Configuration, operation and test data can be set and updated by this command. As for every Monitor channel Table 10:
COD5 0 0 0 0 1 0 1 COD4 0 0 0 1 0 1 0 COD3 0 0 1 1 0 1 0 COD1 0 1 0 1 0 0 1
If R/W = 1 LSEL1 LSEL0 0 0 0 1
1
0
1
1
SOP *: during the on going SOP command SOP* is the previously processed SOP command.
COD0 1 1 1 1 1 1 1
ADDRESS Filter B Filter R Filter X Filter GR Filter GX Filter KA, KD Filter Z
Following Bytes 14 8 8 1 1 2 6
Filters coefficients must be evaluated using a proper ST simulation software.
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STLC3040
4.8 Configuration Registers As already mentioned, Configuration Registers are set and read by SOP command. CR1 sets SLIC kit operating features and some test features.
BIT7 PD BIT6 N/BB BIT5 LB BIT4 TON BIT3 HIA BIT2 HIB BIT1 BIT0 DHP COR XVA OKTON OKTTX OKRNG TMN NOSL IO1 IO2
Reset value: 00h XVA Internal measurement results shown in the following three bits are or not valid (read only) = 0 the following 3 ok-bits are not valid = 1 the following 3 ok-bits are valid OKTON Test Tone meaurement information (read only), see test mode 7 = 0 Test tone level out of defined range = 1 Test tone level in defined range OKTTX Test teletax metering information (read only), see Test Mode D and E = 0 Test teletax metering different from the defined value = 1 Test teletax metering equal to the defined value OKRNG Test Ring tone information (read only), see Test Mode C = 0 Ring tone level out of defined range = 1 Ring tone level within the defined range. TMN Enables or disables COFISLIC testmodes (see chapter 6) = 0 stops the assigned tests (normal mode) = 1 starts the assigned tests selected by Register CR5 NOSL Defines if the shaping of teletax signal is switched On or Off = 0 Teletax shaping is on = 1 Hard switch of Teletax signal IO1 Selection for programmable I/O pin IO1 = 0 sets pin IO1 as input = 1 sets pin IO1 as output IO2 Selection for programmable I/O pin IO2 = 0 sets pin IO2 as input = 1 sets pin IO2 as output CR3 sets Persistence Check for upstream signalling: Off-Hook and Ground-Key.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 DUP3 DUP2 DUP1 DUP0 DUB3 DUB2 DUB1 DUB0
Reset value = 00 h. PD sets the kit either in Stand By or External Indication/Loop open (for further details please see table 13 pag. 45) = 0 SLIC kit (STLC3040/HV (L3000N, L3000S, STLC3170)) in External Indication Mode = 1 SLIC kit (STLC3040/HV (L3000N, L3000S, STLC3170)) in Stand By Mode N/BB sets COFISLIC Battery Mode = 0 Normal Battery = 1 Boosted Battery LB enables Loop Back functions for on chip test = 0 normal function (no loop back) = 1 Loop Back as defined in CR4 register TON enables 1KHz test tone generator = 0 Test Tone Generator Off = 1 Test Tone Generator On HIA and HIB set tip and ring status in active and standby mode
HIA 0 0 1 1 HIB 0 1 0 1 Standby TIP RING normal normal negative Hiz Hiz normal Hiz normal normal TIP Active RING normal Hiz normal normal
normal normal negative Hiz normal
DHP enables High-Pass filter for test purpose = 0 High Pass filter On = 1 High Pass filter Off COR cuts off Receive Path for test purpose = 0 Receive Path transmission is enabled = 1 Receive Path is disable CR2 enables or disables Test Mode, Teletax Signal Shaping Mode and sets the I/O pin direction. The high nibble is only readable and defines test mode results.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
Reset value: A5 h Persistence Reset value is 10 ms both for OffHook and I1 input pin. 20ms for Ground-Key.
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STLC3040
Figure 9.
I1
I1 AFTER PERSISTENCE CHECK ON UPSTREAM 0 N-1ms Nms
I1 I1 AFTER PERSISTENCE CHECK ON UPSTREAM N-1 0 N
D96TL264
DUP3-DUP0 Persistence check for signalling upstream Off-Hook and I1. New status information will be transmitted upstream, after it has been stable for from (N-1) to N millisecond (see fig. 9). N is programmable in range of 1 to 15 ms in steps of 1 ms. DUP3-DUP0 = 0000 means no persistence check. DUB3-DUB0 Persistence check for signalling upstream Ground-Key. New status information will be transmitted upstream, after it has been stable for N millisecond. N is programmable in range from 0 to 60 ms in steps of 4 ms. DUB3-DUB0 = 0000 means no persistence check. CR4 enables internal filters B, Z, X, R, GX/GR. It also programs the Loop Back and sets the codification law: A-law or -law.
BIT7 BIT6 BIT5 BIT4 B Z X R BIT3 BIT2 BIT1 BIT0 GX/GR LOOP1 LOOP0 A/U
Reset value: F9h B represents B-filter = 0 B-filter is Off, Related Transfer Function is zero (HB = 0) = 1 B-filter is On, Related Transfer Function (HB) is defined by programmed filter coefficients (COP command) Z represents Z-filter = 0 Z-filter is Off, Related Transfer Function is zero (HZ = 0) = 1 Z-filter is On, Related Transfer Function (HZ) is defined by programmed filter coefficients (COP command) X represents X-filter = 0 X-filter is Off, Related Transfer Function (HX = 1) is one = 1 X-filter is On, Related Transfer Function
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(HX) is defined by programmed filter coefficients (COP command) R represents R-filter = 0 R-filter is Off, Related Transfer Function (HR = 1) is one = 1 R-filter is On, Related Transfer Function (HR) is defined by programmed filter coefficients (COP command) GX/GR represents GX/GR-filter = 0 GX/GR-filter is Off, Related Transfer Function (HGX/GR = 1) is one = 1 GX/GR-filter is On, Related Transfer Function (HGX/GR) is defined by programmed filter coefficients (COP command) LOOP1-LOOP0 select the loop back (see Block Diagram fig. 3 and paragraph 4.42) = 00 No loop-Back = 01 Loop-Back only GCI interface (LB1 on). = 10 Loop-Back the digital part (Digital Sigma-Delta converter is included, LB2 on). = 11 Loop-Back the Analog part (Analog Sigma-Delta converter is included, LB3 on). A/U chooses coding law = 0 -law coding = 1 A-law coding CR5 sets ring-trip thresholds and test modes
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 RTV3 RTV2 RTV1 RTV0 TESM3 TESM2 TESM1 TESM0
Reset value: 60h. RTV3-RTV0 set Ring-Trip Threshold Value. This value is programmable in the range from 9.6/16 mA to 9.6 mA in steps of 9.6/16 mA.
STLC3040
= 0h corresponds to 9.6/16 mA = Fh corresponds to 9.6 mA For further details please see parameters IRNGGTH (pag 34) TESM3-TESM0 select the testmode.
= 0h = 1h = 2h = 4h = 5h = 7h = 8h = 9h = Ah = Ch = Dh = Eh = Fh No-Test TST-LEAK [CR8.1 = 0, CR5(3:0) = 01h] TST-LKA [CR8.1 = 0, CR5(3:0) = 02h] TST-800Hz TST-TONE-CAL TST-ALB DON'T USED TST-LINE-IMPDC TST-LINE-IMPAC TST-IRING TST-PTTX TST-TTXFILT TST-ILIM
threshold in Stand-by mode. Programmable range is from 0mA to 69.3mA in steps of 1.1mA. = 0000 corresponds to 0mA = 1111 corresponds to 69.3mA At reset the value will be 7.7mA. PDDIS used for state setting as per table 14 (pag 45) RTEN enables Ring-trip in test mode TST-IRING = 0 Ring-trip disabled = 1 Ring-trip enabled CR8 sets synthesized feeding resistance, TTX frequencies. The least significant bit sets the ringing source: internal or external.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
TMM RFED2 RFED1 RFED0 TTX12 TTXNO SOREV XRNG
Every test will be described in Chapter 6 CR6 sets current limitation values and off-hook threshold in Active mode.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 ILIM5 ILIM4 ILIM3 ILIM2 ILIM1 ILIM0 ITHR FIXC
Reset Value: 51h ILIM5-ILIM0 Set Current Limit in Active mode. Current Limit is programmable in range of 0mA to 69.3mA in steps of 1.1mA. = 000000 corresponds to 0mA = 111111 correspondso to 69.3mA ITHR Defines Off-Hook threshold value in Active mode = 0 Threshold at 10mA = 1 Threshold at 13mA Loop indication is set if a loop current greater than 10mA or 13mA is detected. FIXC, COFISLIC uses either fixed coefficients or programmed ones. = 0 Programmed coefficients used = 1 Fixed coefficients used (see paragraph 4.5.2) CR7 sets current-limit value and Off-Hook threshold in Stand-By mode.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
PDSV5 PDSV4 PDSV3 PDSV2 PDSV1 PDSV0 PDDIS RTEN
Reset Value: 00h RFED2-RFED0 Values of the synthesized feeding resistance`. DC Synthesis Value = 2 Rp + 2 50 [RFED [2:0] + 1] TTX12 selects Teletax frequencies = 0 16KHz teletax = 1 12KHz teletax TTXNO sets Battery Reversal for metering instead of 16/12KHz pulse =0 Metering with Teletax pulse =1 Metering with Battery reversal SOREV selects hard or soft Battery Reversal = 0 Hard Battery Reversal = 1 Soft Battery Reversal XRNG selects ringing source: internal or external = 0 Internal Ring = 1 Ring signal from EXT pin TMM enables sign modulation at 1kHz square wave of measurement carried out during test mode = 0 No Modulation = 1 Modulation enabled CR9 programs Ring frequency and amplitude.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
RVR RNGF2 RNGF1 RNGF0 RNGV3 RNGV2 RNGV1 RNGV0
Reset Value: 1Ch PDSV5-PDSV0 Set Current Limit and Off-hook
Reset Value: 2F h RVR fixes Ring Voltage Range = 0 Ring Amplitude = 34.4Vrms + RNGV [3:0] x 2.039Vrms = 1 Ring Amplitude = 45Vrms + RNGV [3:0] x 2.66Vrms Reset Value is 65 Vrms
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STLC3040
RNGF2-RNGF0 select Ring frequency value
= 0h = 1h = 2h = 3h = 4h = 5h = 6h = 7h 16.6Hz Ringing Frequency 20Hz Ringing Frequency 25Hz Ringing Frequency 50Hz Ringing Frequency 60Hz Ringing Frequency Ringing Frequency not used Ringing Frequency not used Ringing Frequency not used
Ring Reset Value is 25 Hz RNGV3-RNGV0 fix Ring Voltage programmation step. CR10 sets Teletax Voltage Level.
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
TTXV7 TTXV6 TTXV5 TTXV4 TTXV3 TTXV2 TTXV1 TTXV0
cleared and two things could happen. If the contents of the shadow register differ from the enabled SR (meaning there was at least one toggle of the enabled SR bits between the time when the interrupt bit is set and the TOP READ command), then the SR byte will be latched into the shadow register while the interrupt bit (SLCX) will remain cleared (low) for 2 frames and then will be set high. On the other hand, if the contents of the shadow-register are equal to the enabled SR, then the interrupt bit remains cleared and will be set only by the next event. At reset, the shadow register content mirrors that of SR register. A mask-bit change causes SR to be latched in the shadow-Register, nevertheless the SCLX bit is cleared
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2
HOOK GNDK VB_2M ILIM
BIT1
BIT0
TEMP CLKF COMRX COMTX
Reset Value: FF h TTXV7-TTXV0 Teletax Amplitude [V] = TTXV (7:0) 10Vrms/255. A dc drop (TTXV [7:3] 15mV 40)is applied as indicated in electric specification section. CR11 Bit (7:4) set External-indication threshold
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
X ETHR3 ETHR2 ETHR1 ETHR0 STRES3 TXONE DHPRX
RESET value = 10 h ETHR [3:0] set the External-indication threshold: for ETHR[3:0] = 0h, threshold = 0V; for ETHR[3:0] > 0h: Threshold = 8V + ETHR [3 : 0] 1V TXONE and STRES3 must be always programmed to 0 DHPRX = 1 disable the Rx high pass filter CR12 can mask the effect on SLCX of the six most significant bits of Signalling Register. If a bit is masked it will not affect the SLCX bit of upstream C/I channel. The unmasked SR bits are used to trigger an event-detect circuit and will latch the SR signals into a shadow register whenever an event occurs. An event is defined as a toggling of one or more of the enabled SR bits. Once the interrupt is set and the shadow registers are latched, any further event does not influence the interrupt or the shadow registers. With the SR TOP READ command, the byte representing the SR will be sent out to the DU depending on the values of the MASK bits. For unmasked SR bit its shadow register bit is sent out; otherwise the value of SR bit is sent out. At the end of the readout of the above byte, the interrupt bit is
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Reset Value: FFh HOOK Mask bit for Hook information in the signalling register = 1 No influence on SLCX bit (Upstream C/I.5) = 0 Each change of the HOOK bit sets SLCX bit (Upstream C/I.5) GNDK Mask bit for Ground Key information in the signalling register = 1 No influence on SLCX bit (Upstream C/I.5) = 0 Each change of the GNDK bit sets SLCX bit (Upstream C/I.5) VB_2M Mask bit for half-battery information in the signalling register = 1 No influence on SLCX bit (Upstream C/I.5) = 0 Each change of the VB_2 bit sets SLCX bit (Upstream C/I.5) ILIM Mask bit for current limit information in the signalling register = 1 No influence on SLCX bit (Upstream C/I.5) = 0 Each change of current limit bit sets SLCX bit (Upstream C/I.5) TEMP Mask bit for temperature information in the signalling register = 1 No influence on SLCX bit (Upstream C/I.5) = 0 Each change of the temperature bit sets SLCX bit (Upstream C/I.5) CLKF Mask bit for clock-fail information in the signalling register = 1 No influence on SLCX bit (Upstream C/I.5) = 0 Each change of the clock-fail bit sets SLCX bit (Upstream C/I.5) COMRX = 0 Linear code in Rx is enabled = 1 PCM in Rx is Enabled COMTX = 0 Linear code Tx is enabled = 1 PCM in Tx is enabled
STLC3040
4.9. COFSLIC PROGRAMMING PROCEDURE SOP - Write Commands
DD Address SOP-Write 0 Byte DD Address SOP-Write 2 Bytes CR1 CR2 DD Address SOP-Write 12 Bytes CR1 : CR12 7 1 6 0 0 6 0 0 5 0 4 0 3 0 0 2 0 1 2 0 1 1 0 0 1 0 0 0 1 0 0 1 1 Bit 7 6 5 4 Idle Idle Bit 7 6 5 4 Idle Idle Idle Idle Bit 7 6 5 4 Idle Idle Idle : Idle 3 2 1 0 DU 3 2 1 0 DU 3 2 1 0 DU
7 1
5 0
4 0
3 0 0 Data Data
7 1
6 0 0
5 0
4 0
3 0 0 Data : Data
2 0 1
1 0 1
0 1 0
COP - Write Commands
DD Address COP-Write 8 Bytes Coeff. 1 : Coeff. 8 7 1 X 6 0 0 5 0 0 4 0 0 3 0 0 2 0 0 1 0 1 0 1 1 Bit 7 6 5 4 Idle Idle Idle : Idle 3 2 1 0 DU
Data : Data
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STLC3040
SOP - Read Commands
DD Address SOP-Read 7 1 X 6 0 1 5 0 X 4 0 X Idle Idle Idle 3 0 0 2 0 1 1 0 0 0 1 0 1 0 0 0 0 0 Bit 7 6 5 4 3 Idle Idle 0 0 0 1 0 1 Address SOPK-1 2 1 0 DU
(*) (*) LSEL1 LSEL0
DD Address SOP-Read
7 1 X
6 0 1
5 0 X
4 0 X Idle Idle Idle Idle
3 0 0
2 0 1
1 0 0
0 1 1
Bit
7
6
5
4
3 Idle Idle
2
1
0
DU
1
0
0
0
0 0 Data Data
0 1
0
1
Address SOPK-1 CR1 CR2
(*) (*) LSEL1 LSEL0
DD Address SOP-Read 12 Bytes
7 1
6 0 1
5 0
4 0
3 0
2 0 1
1 0 1
0 1 0
Bit
7
6
5
4
3 Idle Idle
2
1
0
DU
Idle Idle Idle : Idle
1
0
0
0
0 0 Data : Data
0 1
0
1
Address SOPK-1 CR1 : CR12
(*) (*) LSEL1 LSEL0
(*) LSEL1, LSEL0 of previous SOP processed command, SOPK-1 is former SOP command
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STLC3040
TOP - Read Commands
DD Address TOP-Read 1 Byte 7 1 X 6 0 1 5 0 X 4 0 X Idle Idle 3 0 1 2 0 1 1 0 0 0 1 0 1 0 0 0 Bit 7 6 5 4 Idle Idle 0 0 0 1 Address SR 3 2 1 0 DU
Data
DD Address TOP-Read 3 Bytes
7 1 X
6 0 1
5 0 X
4 0 X Idle Idle Idle Idle
3 0 1
2 0 1
1 0 0
0 1 1
Bit
7
6
5
4 Idle Idle
3
2
1
0
DU
1
0
0
0
0
0
0
1
Address SR CKS1 CKS2
Data Data Data
DD Address TOP-Read 15 Bytes
7 1 X
6 0 1
5 0 X
4 0 X Idle Idle : Idle
3 0 1
2 0 1
1 0 1
0 1 0
Bit
7
6
5
4 Idle Idle
3
2
1
0
DU
1
0
0
0
0
0
0
1
Address IDCOD0 : IDCOD14
Data : Data
COP - Read Commands
DD Address COP-Read 8 Bytes 7 1 X 6 0 1 5 0 0 4 0 0 Idle Idle : Idle 3 0 0 2 0 0 1 0 1 0 1 1 1 0 0 0 Bit 7 6 5 4 Idle Idle 0 0 0 1 Address Coeff. 1 : Coeff. 8 3 2 1 0 DU
Data : Data
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STLC3040
5. APPLICATION & EXTERNAL COMPONENTS LIST Typical COFISLIC application is shown in Fig. 5. It shows the HV (L3000N, L3000S, STLC3170) driving the phone line and interfacing the COFISLIC with the external components summarized in the following table. Table 11:
Ref RREF RAC Typ. Value 37.2k 1% 1620 1% Function Bias resistor (Iref) @ VDD AC reference impedance DC reference impedance AC/DC current splitting Protective Shottky Diode Battery Reversal Capacitor Battery Voltage Rejection
820 1% RDC CAC (*) 11F 5V 20% DS CAP CDVB BAT 49 100nF 47F - 20V 20%
If CR1.2 = 0, CR1.3 = 0, line current is measured allowing line resistance and capacitance to be obtained. If CR1.2 = 1, CR1.3 = 0, TIP wire leakage to ground is measured with RING wire in high impedance. If CR1.2 = 0, CR1.3 = 1, RING wire leakage to ground is measured with TIP wire in high impedance. Measured value, available on Tx B1 byte: It RDC / / CAC Tx GAIN 50 6 It = transversal line current RDC = DC reference resistance (typically 820) CR8.0 = 1 Active Modulation for returned value.
Operating Mode: B filter: Z filter: Rx Path: Tx Path: Test dedicated, H.V. Active Off Off Functional Functional with input connected to RDC resistance. Programmable Programmable (suggested max value to avoid saturation = 0800h) Off Not Applicable Only 1KHz Available As in Active Mode Off Controlled by CR1.1 set by SOP register Command set by CR1 register
(*) unbiased capacitor
L3000N and L3000S require dotted components (see fig. 5) for Off/Hook detection in "External Indication" (see table 12). Table 12:
Ref RT, RR Typ. Value 33k Function Line Feed
R, X, GX, GR Filters: KD filter:
DC Synthesis:
6. INTEGRATED TEST FEATURES The device has built-in several functionalities dedicated to perform generic testing. Each test is enabled if CR2.3 (TMN) bit is set to 1. In each test description more details about active functionalities are written. 6.1.1. LINE TEST MODE 1 (TST-LEAK) Enabled by CR2.3 = 1 and CR5 (3:0) = 01h and CR8.1 = 0. A trapezoidal signal (see Fig. 10) is sent to 2-wire line. Figure 10.
GND VDROP VPP
T1 T2 T3 T4
D95TL206C
TTX: Internal Tone Generation in Rx: Hook Detection: ILIM High-Pass Filters: Reverse Polarity Boosted Battery
6.1.2. LINE TEST MODE 2 (TST-LKA) Enabled by CR2.3 = 1, CR5 [3:0] = 02h and CR8.1 = 0. The setup is the same of Test 1 except the measured value that is: It RDC Tx GAIN 6 50 If CR1.2 = 1, CR1.3 = 0, TIP wire leakage to ground is measured with RING wire in high impedance. If CR1.2 = 0, CR1.3 = 1, RING wire leakage to ground is measured with TIP wire in high impedance.
T1=T2=T3=T4=100ms VDROP = -170mV - 15 CR10[7:3] VPP = 25 V if CR9.7=0 40 32.7 V if CR9.7=1 VPP = 40 17 VOUT = (VPP + VDROP + RX) = if CR 9.7 = 1 13
VOUT = (VPP + VDROP + RX) = 1 if CR 9.7 = 0
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STLC3040
6.1.4. TEST MODE 4 (TST-800Hz) The device is in Active mode. An 800Hz tone is injected into the line. The tone amplitude is programmable through TTX voltage register (CR10). 1KHz tone can be added (CR1.4), in this case Rx input is disabled. 6.1.5. TEST MODE 5 (TST-TONE-CAL) It carries out a tone calibration. 1KHz frequency is sent to backplane (TX direction) Returned Information on Tx B1 byte: 1KHz Tone at the maximum digital level
Operating Mode: B filter: Z Synthesis: Rx Path: Tx Path: R, GR Filters: DC Synthesis: TTX: Internal Tone Generation in Rx: ILIM: Hook Detection: High Pass Filters: Active Programmable Programmable Functional Off Gain as per programmed coefficients On Functional 1KHz available On As in Active Controlled by CR1.1 and CR11.1 DC Synthesis:
When this Test mode is on, all the functionalities of Active mode are still available. In addition the window detector is switched on. 6.1.7. TEST MODE 9 (TST-LINE-IMPDC) In this mode thr Rx channel is functional and its gain is increased by a factor 16 (the same gain is also applied to the 1KHz enabled by CR1.4). Z, ILIM and DC feed characteristics are disabled. A drop of roughly 3.9V/step is superimposed to the line under control of CR10 [7:3]. Tx path is fully functional and controllable. Transversal line current (It) is measured across the parallel RDC, CAC: RDC It CAC Tx GAIN 50 6 Modulated if TMM = 1 in CR8 register.
Operating Mode: B Filter: Z Filter: Rx Path: Tx Path: R, X, GR, Gx: KD: Test Dedicated, H.V. set by downstream C/I Programmable Off Functional Functional Programmable Programmable (Suggested max. value to avoid saturation = 800h) Only Programmable Voltage drop Not Applicable 1KHz available As in active mode As per programmed value in Active mode Controlled by CR1.1 and CR11.1 Set by SOP register command
6.1.6. TEST MODE 7 (TST-ALB) A 1KHz Tone can be generated in digital section. This Test mode is equivalent to the Active mode. Disabling B filter, the gain of the whole path (Rx + HV (L3000N, L3000S, STLC3170) + external load + Tx) can be measured. The measurement is carried out by a window detector placed at the input of the PCM encoder. The window detector compares the negative or positive amplitude peak (it depends on the programmed battery polarity) of the input signal with a range of values. The range is centred around 6dB below the PCM full scale. Range width is 0.5dB or 1.5dB depending on the programmed polarity. Returned information on upstream GCI channel: It RAC Tx GAIN 1. 50 2. CR2.6 (OKTON) 3. CR2.7 (XVA) = 1means measurement has settled CR2.6 = 1 means signal level within the window range.
TTX: Internal Tone Generation in Rx: Hook detection: ILIM High Pass Filters Reverse Polarity
6.1.8. TEST MODE A (TST-LINE-IMPAC) This test follows the same procedure as Test 9 having the sensing done only on RDC. Measured value:
RDC it Tx GAIN 50 6
6.1.9. TEST MODE C (TST-IRING) Normal Ring signal (no power reduced mode available) is generated and sent to 2-wire in order to test internal ring generator. Frequency and Amplitude are programmable by CR5 register. Auto Ring Trip function can be disabled by RTEN
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STLC3040
bit (CR7 Register). The Hook state is anyway sent upstream. Returned Information on upstream GCI channel: It RDC Tx GAIN 1. 50 6 2. CR2.4 (OKRNG) OKRNG = 1 means that ring amplitude is within the accepted range see fig. 11. 3. CR2.7(XVA) = 1 means measurement has settled. Modulated if TMM = 1 in CR2 Register. Figure 11: VRDC sign depending on Battery Polarity.
VRDC VRDC Sign depending on Battery Polarity
quently about the functionalities of TTX generation circuitry. 800Hz frequency is used instead of standard 12KHz/16KHz, because 12KHz or 16KHz would be cut out by filters in Tx path. Returned Information on TXB1 channel: It RAC GTX 50
Operating Mode: B filter: Z filter: Rx Path: Tx Path: R, X, GR, Gx: KD: Active Programmable Programmable Functional Functional Programmable Programmable (suggested max value to avoid saturation = 800h Functional 800Hz with programmable amplitude 1KHz Available As in active Functional Controlled by CR1.1 and CR11.1
DC Synthesis:
RING PAUSE
D95TL207A
TTX: Internal Tone Generation in Rx: Hook detection: ILim: High Pass Filters:
RING BURST
RING AMPLITUDE PEAKS "MEASURED" BY THE WINDOWS DETECTOR
Connecting a known impedance across the line and considering the programmed Ring level (CR9 register), a window detector, as for Test 7, allows to monitor if the signal at PCM encoder input is in the correct range. Through this procedure the ring functionality including several effects, HV device, protect resistor, battery voltage etc, can be evaluated.
Operating Mode: B Filter: Z Filter: Rx Path: Tx Path: X, Gx: KD: Ring Off Off Off Functional Programmable Programmable (Suggested max value to avoid saturation = 800h) Off Not applicable Not applicable As in Ring Mode Off Controlled by CR1.1 and CR11.1
6.1.11. TEST MODE E (TST-TTXFILT) Purpose of this test is to check the functionality of the TTX filter. A TTX signal at 12kHz or 16kHz superimposed to a 1KHz tone, enabled by CR1.4, is sent to the line. Returned Information on upstream GCI channel: It RAC Tx GAIN 50 2. CR2.5 (OKTTX) 1. 3. CR2.6 (OKTON) 4. CR2.7(XVA) = 1 means measurement has settled. OKTTX says that programmed TTX level has been caught up. OKTON set to 1 indicates that 1kHz tone has not been compressed by the superimposed TTX signal. In this case the TTX filter properly works.
Operating Mode: B Filter: Z Filter: Tx Path: Rx Path: R, X, GR, GX KD: Active Programmable Programmable Functional Functional Programmable Programmable (suggested max value to avoid saturation = 800h
DC Synthesis: TTX: Internal Tone Generation in Rx: Hook detection ILIM: High Pass Filters:
6.1.10. TEST MODE D (TST-PTTX) 800Hz tone is sent to 2-wire. This pseudo TTX signal (800Hz) requires C/I.5 bit (TIM) set to 0. Shaping functions are disabled. The internal window detector is enabled as for Test Mode 7. Measured line current gives information about amplitude of generated pseudo TTX and conse28/49
STLC3040
DC Synthesis: TTX: Internal Tone Generation in Rx Hook detection ILIM High Pass Filter Functional ON with programmable amplitude and frequency. 1KHz available As in Active Mode Functional Controlled by CR1.1 and CR11.1 Operating Mode: B Filter: Z Filter: Tx Path: Rx Path: R, X, GR, Gx KD: Test Dedicated, H.V. Active Off Off Functional Functional with input connected to RDC resistance. Programmable Programmable (Suggested max value to avoid saturation = 800h) Functional Not applicable 1kHz available As in Active Mode Functional Controlled by CR1.1 and CR11.1 Set by SOP register command Boosted Battery
6.1.12. TEST MODE F (TST-DC LOOP) Purpose of this test is to check if DC characteristics (RFEED and ILIM) synthesis works correctly. A trapezoidal signal (see Fig. 10) is sent to the 2wire line. Returned information on Tx B1 byte: It 50 RDC CAC 6 Tx GAIN
DC Synthesis: TTX: Internal Tone Generation in Rx: Hook detection: ILIM: High Pass Filters: Reverse Polarity:
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STLC3040
ABSOLUTE MAXIMUM RATINGS (*)
Symbol Vdd VCC VEE AGND to DGND VCC to VDD ILTH Parameter Positive Digital Supply Voltage Referred to DGND Positive Analog Supply Voltage Referred to AGND Negative Analog Supply Voltage Referred to AGND Difference AGND to DGND Difference VCC to VDD DC input and output current at any input or output pin (free from latch-up) Maximum Junction Temperature Storage Temperature Range Voltage Referred to DGND Test condition Min. -0.3 -0.3 -5.5 -0.3 -0.3 Max. +5.5 +5.5 +0.3 +0.3 +0.3 100 Unit V V V V V mA
Tj Tstg VIGCI VOGCI VTHVI IPDN VLINT VCHVI VBHVI V2WI VDIO VMIS VDUN VTID VBID VCREV VACDC
Voltage Referred to AGND Input Current Voltage Referred to AGND
Voltage Referred to AGND Voltage Referred to DGND
Voltage Referred to AGND
VOREF VAUN
Input GCI pins 3, 4, 5, 40, 41, 42 and 43 Output GCI pin 6 Interface to H.V. pins: 9, 10 Interface to H.V. pin: 28 Interface to line pins: 11,12 Interface to H.V. Current Input pins: 15, 19 Voltage Reference Input pin: 25 Ouput Buffer pin: 26 I/O pins: 7, 8, 38, 39 Ring Sync pins: 29, 36 Reserved pins: 37, 44 Identification Code pins:31, 32 Identification Code pin: 35 Battery Reversal capacitor input pin: 14 AC and DC - synthesis Reference Resistor pins 16, 22 AC/DC line split pin: 20 AC splitter capacitor pin: 21 Reference Voltage output pin: 23 Reserved pins: 13, 17, 18, 24, 30
150 -55 -0.3 -0.3 VEE -0.3 -0.5 -80 VEE -0.3 VEE -0.3 VEE -0.3 -0.3 -0.3 -0.3 VEE -0.3 -0.3 VEE -0.3 -3 VEE -0.3 -0.3 -0.3 -0.3
+150 VDD +0.3 VDD +0.3 VCC +0.3 0.5 80 VCC +0.3 VCC +0.3 VCC +0.3 VDD +0.3 VDD +0.3 VDD +0.3 VCC +0.3 VCC +0.3 +0.3 +3 VCC +0.3 +0.3 VCC +0.3 VCC +0.3
C C V V V mA V V V V V V V V V V V V V V V
(*) Stresses in excess of those listed under "Absolute Maximum Rate" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions in excess of those indicated in the operational sections of this specification is not implied.
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient Max. Value 60 Unit C/W
OPERATING RANGE
Symbol VDD VCC VEE DGND to AGND Top 30/49 Parameter Positive Digital Supply Voltage Referred to DGND Positive Analog Supply Voltage Referred to AGND Negative Analog Supply Voltage Referred to AGND Difference AGND to DGND Ambient Operating Temperature Value 4.75 to 5.25 4.75 to 5.25 -4.75 to -5.25 0 -40 to +85 Unit V V V V C
STLC3040
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS (Tamb = 0 to 70C, VDD = VCC = 5V 5%, VEE = -5V 5%, AGND = DGND = 0V; for operating in ext. temp. range -40 +85C the same limits are confirmed by characterisation data unless otherwise specified.)
Symbol Vil Vih Ii Vol Voh VT+ VTVH VOLOD Vhv1, Vhv2 Vmv1, Vmv2 Vlv1, Vlv2 VihID ViIID VimID Parameter Input Voltage at Logical "0" Input Voltage at Logical "l" Input Current Output Voltage at Logical "0" Output Voltage at logical "l" Positive going Threshold Negative going Threshold Threshold Hysteresis Output Voltage at Logical "0"on open drain output Output Voltage at High Level on pins 9, 10 Output Voltage at Zero Level on pins 9, 10 Output Voltage at Low Level on pins 9, 10 Ternary input pins 31, 32 High level Ternary input pins 31, 32 Low level Ternary input pins 31, 32 medium level pin: 6, IO = 7.5mA pin 10: IO = 10A pin 9: 10A IO 300A pin 10: IO = 10A pin 9: 10A IO 300A pin 10: IO = 10A pin 9: 10A IO 300A 2 -1 -5 2 VEE -1 Test Condition Pins 29,35,36,38,40,41,42,43. Pins 7, 8 [when inputs] Pins 29,35,36,38,40,41,42,43 Pins 7, 8 [when inputs] 0V < Vin < VDD Pin 7, 8 (when outputs), 39 IOl = 4mA Pin 7, 8 (when outputs), 39 IOh = -3mA pins: 3, 4, 5 1.35 0.5 0.45 5 1 -2 VCC -2 1 VDD-0.45 3.15 Min. 0 0 VDD-1.5 VDD-1.5 -1 1 0.45 Typ. Max. 1.5 1.5 Unit V V V V A V V V V V V V V V V V V 2 2 1 Notes
(1) for all the digital inputs: TTL, CMOS, 3-Levels, with Hysteresis. Except pins 18, 24, 30, 44, 43, which have internally 22K pull-down. (2) see figure 12.
Figure 12.
VOUT HIGH
LOW
VT-
VT+
VIN
D96TL255A
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STLC3040
SUPPLY CURRENTS: see Table 13 with coefficient and configuration register contents set as per default values after reset; Tamb = 0 to 70C, VDD = VCC = 5V 5%, VEE = -5V 5%, AGND = DGND = 0V. Typical values are measured at Tamb = 25C, VDD = VCC = 5V, VEE = -5V ; for operating in ext. temp. range -40 +85C the same limits are confirmed by characterisation data unless otherwise specified.
VOLTAGE SUPPLY OPERATING MODES ACTIVE VDD IDDACT Min Typ 8mA Max 13mA IDDPDEN Min Typ Max 3mA IDDRNG Min Typ Max 13mA IDDSTB Min Typ Max 7mA VCC ICCACT Min Typ Max 23mA ICCPDEN Min Typ Max 5mA ICCRNG Min Typ Max 23mA ICCSTB Min Typ Max 13mA VEE IEEACT Min Typ Max 23mA IEEPDEN Min Typ Max 2mA IEERNG Min Typ Max 23mA IEESTB Min Typ Max 10mA
POWER DENIAL
RING
STAND-BY
DC ELECTRICAL CHARACTERISTICS OF ANALOG PINS (Tamb = 0 to 70C, VDD = VCC = 5V5%, VEE = -5V 5%, AGND = DGND = 0V; for operating in ext. temp. range -40 +85C the same limits are confirmed by characterisation data unless otherwise specified)
Symbol IPDOHiZ IPDOLOZ VPDO VL1, VL2 Itmax Ilmax VBIM VOUT ZVOUT IVOUT RAC, CAP, ACDC,CAC, RDC, REF Parameter Leakage Current at pin 28 in High impedance Sinked Current at pin 28 in low impedance Operating Voltage at pin 28 Operating Voltage at pin 11, 12 Absolute Value of Input Current at pin 19 Absolute Value of Input Current at pin 15 Battery Image Voltage 2-wire Ouput Voltage 2-wire Output Impedance 2-wire Output Current see External Component List -3.5 -3.3 200 -1 1 Test Condition VPDO = +1.0V VPDO = +1.0V Min. -1 45 0 -70 Typ. Max. 1 55 5 +70 2.6 2.6 0 3.3 Unit A A V V mA mA V V mA
DC ELECTRICAL CHARACTERISTICS OF ANALOG PINS (Tamb = 0 to 70C, VDD = VCC = 5V5%, VEE = -5V 5%, AGND = DGND = 0V; for operating in ext. temp. range -40 +85C the same limits are confirmed by characterisation data unless otherwise specified) Active Mode (see Table 13)
Symbol VOUTDROP Parameter Operation Dropout Voltage on pin 26 Operation Dropout Voltage on pin 26 RFEED DC feeding resistance on pin 26 Test Condition It = 0 DD (pin 5): Idle CR1.6 (N/BB) = 0 It = 0 DD (pin 5): Idle CR1.6 (N/BB) = 1 It < Ilim/50 DD (pin 5): Idle CR1.6 (N/BB) = X Min. VOUT1 -30 -725 Typ. VOUT1 Max. VOUT1 +30 -645 Unit mV Notes 1
-685
mV
RFEED1 RFEED1 RFEED1 -10% +10%
2
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STLC3040
DC ELECTRICAL CHARACTERISTICS OF ANALOG PINS (continued)
Symbol RFEEDL Parameter DC feeding resistance in limited current pin 26 Test Condition It Ilim/50 DD (pin 5): Idle CR1.6 (N/BB) = X Programmable Limitation CR1.6 (N/BB) = 0 current on pin 19 CR1.6 (N/BB) = 1 It < 1mA Programmable off-hook CR6.1 (ITHR) = 0 0 < Tamb < 70C threshold for positive SOP.5 (POL) = X -40 < Tamb < +85C transition on pin 19 CR6.1 (ITHR) = 1 0 < Tamb < 70C SOP.5 (POL) = X -40 < Tamb < +85C Programmable off-hook CR6.1 (ITHR) = 0 0 < Tamb < 70C threshold for negative SOP.5 (POL) = X -40 < Tamb < +85C transition on pin 19 CR6.1 (ITHR) = 1 0 < Tamb < 70C SOP.5 (POL) = X -40 < Tamb < +85C Off-hook persistency check CR6.1 (ITHR) = X Ground-key bit current SOP.5 (POL) = X threshold for positive transition on pin15 Ground-key threshold for negative transition Ground-key persistence check Current drained for SR.3 (TEMP) = 0 thermal overload from pin9 SR.3 (TEMP) = 1 Thermal overload hysteresis Voltage on pin25 to toggle See test conditions 8 the SR.5 bit (VB_2) C/I.6 (conv) = 1 SOP.5 (POL) = 0 Limiting current, thermal overload, half battery bit persistence Min. 15 Typ. Max. Unit k Notes
ILIM/50
-10% -10% 180 175 234 225 160 155 214 205 |140|
IL1 IL1 200 195 260 255
+10% +10% 220 220 286 286
mA mA A A A A A A A A ms A A
3 3
IPOFF-HK
INOFF-HK
OFFHKPERS IPGNDK
NH |240|
4
INGND GNDKPERS Ithv HITHV VB/2
|120| NG 180 800 20 VBIMT VBIMT VBIMT -20% +20% 5.5 8.5
ms A A A V
5
320
SRBITPERS
ms
Stand-By Mode (see Table 13)
Symbol VODROPSBY RFEEDSBY RFEEDL Parameter Stand-by Dropout Voltage on pin 26 DC feeding resistance on pin 26 Stand-by DC feeding resistance in limited current pin 26 Programmable limitation current in stand-by on pin 19 Stand-by programmable off-hook threshold on pin 19 Stand-by off-hook persistence check Stand-by ground-key bit current threshold for positive transition on pin 15 Stand-by ground-key persistence check Current drained for thermal overload from pin 9 in stand-by Test Condition It = 0A It < Ilim/50 It Ilim/50 Min. -85 Typ. -70 Max. -55 Unit mV k A A ms |240| A Notes
-10% RFEED1 +10% 15
2
ILIM/50SBY IOFF-HKSBY OHKSBYPERS ISBYGNDK
-10% -10%
ILSBY ILSBY NH
+10% +10%
6 6 4
|140|
GNDSBYPERS ISBYthv
NG SR.3 (TEMP) = 0 SR.3 (TEMP) = 1 180 800 8.5
ms A A ms
5
320 5.5
SRSBYBITPERS Limiting current, thermal overload, half battery bit persistence in stand-by
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STLC3040
DC ELECTRICAL CHARACTERISTICS (continued) Ring Mode (Downstream C/I.7 [RING] = 1 see Table 13)
Symbol VODROPRNG Parameter Ring mode Dropout Voltage on pin 26 Ring On Ring mode Dropout Voltage on pin 26 Reduced Power Ring Pause Ring mode Dropout Voltage on pin 26 Ring Pause Ring mode DC feeding resistance on pin 26 Ring DC feeding resistance in limited current on pin 26 Programmable limitation current on pin 19 in reduced power ring pause Ring mode off-hook persistence check Ring mode ground-key persistence check Current drained for thermal overload from pin 9 in ring mode Test Condition Downstream C/I.5 (TIM) = 1 & C/I.6 (CONV) = X Downstream C/I.5 (TIM) = 0 & C/I.6 (CONV) = 0 Downstream C/I.5 (TIM) = 0 & C/I.6 (CONV) = 1 Downstream C/I.5 (TIM) = 0 & C/I.6 (CONV) = 1 It < Ilim/50 It Ilim/50 Downstream C/I.5 (TIM) = 0 & C/I.6 (CONV) = 0 Min. -20 Typ. Max. 20 Unit mV Notes
-85
-70
-55
mV
-20
20
mV k
RFEEDRNG RFEELRNG ILIM/50RNG
-10% 15 -10%
0
+10%
2
ILSBY
+10%
A
6
OHKRNGPER GNDRNGPER ISBYthv
NH NG SR.3 (TEMP) = 0 Downsteam C/I.5 (TIM) = 0 & C/I.6 (CONV) = 0 SR.3 (TEMP) = 1 Downsteam C/I.5 (TIM) = 0 & C/I.6 (CONV) = 0 180
ms ms A
4 5
320
800
A
SRRNGBITPER
IRNGGTH
Limiting current, thermal overload, half battery bit persistence in ring mode Ring trip off-hook current threshold on pin 19
5.5
8.5
ms A
IRNGGNDKTH
Ring ground-key bit current threshold for positive transition on pin15
Downstream C/I.5 (TIM) = 1 & C/I.6 (CONV) = X OR Downsteam C/I.5 (TIM) = 0 & C/I.6 (CONV) = 1 Downsteam C/I.5 (TIM) = 0 & C/I.6 (CONV) = 0 Downsteam C/I.5 (TIM) = X & C/I.6 (CONV) = X
-10%
THR
+10%
7
-10%
ILSBY
+10%
A A
6
|140|
|240|
Power Denial Mode (Downstream C/I.[7,5] [RING, CONV, TIM] = 0, CR1.7 [PD] 0, see Table 13.
DVOFFHKPD CVOFFHKPD Power denial differential voltage off-hook threshold Power denial threshold voltage off-hook common mode range Off-hook persistence check in power denial mode -15% -60 +15% +60 V
OHKPERSPD
CR6.1 (ITHR) = X
NH
ms
4
Notes: (1) VOUT1 = -(170mV + CR10[7..3] 15mV) (2) RFEED1 = (RDC/6.56) (1+CR8 [7..5]) (3) IL1 = (CR6[7..2] 1.1mA)/50
(4) NH = CR3 [7..4] 1ms (5) NG = CR3 [3..0] 4ms (6) ILSBY = (CR7 [7..2] 1.1mA)/50 (7) THR = {(1 + CR5[7..4]) 9.6mA/16}/50
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STLC3040
AC ELECTRICAL CHARACTERISTICS OF ANALOG PINS Tamb = 0 to 70C, VDD = VCC = 5V5%, VEE = -5V 5%, AGND = DGND = 0V (see Table 13); for operating in ext. temp. range -40 +85C the same limits are confirmed by characterisation data unless otherwise specified.
Symbol GX GR THDX THDR Parameter Absolute gain in TX Absolute gain in RX Total harmonic distortion in TX Total harmonic distortion in RX Test Condition see fig. 13 Normal temp. range Extended temp. range see fig. 13 Normal temp. range Extended temp. range see fig. 13; fref = 1kHz; reference signal level 0dBm0 @ digital side; measurements of 2nd and 3rd order harmonics fref = 1kHz; reference signal level @ digital side; -10dBm0 Sinusoidal Test Method; fref = 1kHz; reference signal level @ digital side; -10dBm0 Sinusoidal Test Method; fref = 1kHz; see test cond. 1 Teletax enabled with Downstream C/I.5 (TIM) = 0; ALaw 0 < Tamb < 70C -40 < Tamb < +85C Teletax enabled with Downstream C/I.5 (TIM) = 0; ALaw see test cond. 1 Teletax enabled with Downstream C/I.5 (TIM) = 1; ALaw see test cond. 2, Sinusoidal test method Min. -0.2 -0.4 -0.2 -0.4 Typ. Max. 0.2 0.4 0.2 0.4 -48 -48 Unit dB dB dB dB dB dB
GFTX GFRX GLTX GLRX S/NTX S/NRX NTP
Gain Variation with frequency in TX Gain Variation with frequency in RX Gain Variation with level in TX Gain Variation with level in Rx Signal to noise ratio in TX Signal to noise ratio in Rx Idle channel noise in transmit
see fig.12 see fig.12 see fig.13 see fig.13 see fig.14
-73 -71
-67 12
NRP
Idle channel noise in receive
dBmp dBmp Vp Vp
NTTX-TP
Idle channel noise in receive with metering pulse on output
12
SOSRX SOSTX Thl Arl PSRRP2W
Spurious out of band signals at analog output Spurious out of band signals at digital output Cofislic Transhybrid loss Return loss Positive power supply rejection ratio on 2-wire
-31 -25
dB dB dB dB dB
PSRRPGCI
Positive power supply rejection ratio on data-up GCI
PSRRN2W
Negative power supply rejection ratio on 2-wire
PSRRNGCI
Negative power supply rejection ratio on data-up GCI
see test cond. 3 see test cond. 4 VRIPPLE = 100mV, 300Hz f 3400Hz, on VCC Residual measured on VOUT (pin 26) see test cond. 5 VRIPPLE = 100mV, 300Hz f 3400Hz, on VCC Residual measured on 5GCI data-up DU (pin 6) see test cond. 5 VRIPPLE = 100mV, 300Hz f 3400Hz, on VEE Residual measured on VOUT (pin 26) see test cond. 5 VRIPPLE = 100mV, 300Hz f 3400Hz, on VEE Residual measured on GCI data-up DU (pin 6) see test cond. 5
40 25 -56
-30
dB
-56
dB
-30
dB
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STLC3040
AC ELECTRICAL CHARACTERISTICS OF ANALOG PINS (continued)
Symbol V2WRNG THDRNG VTTX THDTTX Parameter Ring amplitude at 2-wire output VOUT (pin 26) Total harmonic distortion in Ring mode 2-wire amplitude at VOUT (pin 26) during teletax emission Total harmonic distortion during teletax emission Test Condition see test cond. 6 see test cond. 6 see test cond. 7 see test cond. 7 -5% 2W TTX Min. -5% Typ. 2WRNG Max. +5% 2% +5% 2% Vrms Unit Vrms
ABSOLUTE GAIN Rx/Tx (law A)
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = 00 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 50 GR = FFh GX = FFh K = 1000h CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = 03 (255) (255) (4096) target Vout represents the rms level to be measured at Vout starting from a DD Vpcm (dBm0) code with a certain set of coefficient. target Vout = (mVrms) = (2 1.514 2) [10^ ((Vpcm 3.14)/20)]/16 (0.98 (R[1]/8192) (GR/256)/(2 sqr (2)))
Example if DD Vpcm = 0dBm0 target Vout = 45.5mVrms (0dBm0/COFISLIC) absolute gain = 20 log (Vout / target Vout)
target DU represents the dBm0 level expected on DU with a certain set of coefficient and a Vrac of 41.4Vrms VRac_ref is the amplitude of the sine wave (1kHz) to be applied on RAC (pin 16) in order to expect on DU a Vpcm dBm0 level with the same set of coefficient. target DU (dBm0) = 3.14 + 20 Log((0.0414 3 (2 sqr(2)) / 1.514) 16 (K/8192) (X[1]/8192) (GX/256) 0.966) VRac_ref = (41.4mV 10^ ((Vpcm - target DU)/20)
R
| 1000h | 0h | 0h | 0h | 1000h | 0h | 0h | 0h
(4096) | (0) | (0) | (0) | (4096) | (0) | (0) | (0) |
X
B[1..8] = 0 Z[1..3] = 0 Reference frequency = 1kHz
Example if target DU = 0dBm0 then VRac_ref = 32.3mVrms (A_law) absolute gain = dBm0 level on DU (full scale 3.14dBm0 A_law)
Figure 13.
RAC VRAC 1620
DU 16 6 0dBm0
VOUT V2W
DD 26 5 0dBm0
D96TL256A
36/49
STLC3040
FREQUENCY RESPONSE Rx/Tx
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = 00 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 5C GR = 79h GX = 80h K = 1000h | 1DBCh | 1AE6h | 24B8h | 8CCh | 3CFChh | 3F41h | 1476h | 1449h CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = 03 (121) (128) (4096) (7612) | (6886) | (-6984)| (2252) | (-772) | (-191) | (5238) | (5193) |
Multitone on DD (pin 5) total level = -10dBm0 Multitone on VRac (pin 16) total amplitude about 24mVp freq.resp. Rx = 20 log(V2w fx / V2w 1kHz) freq.resp. Tx = dBm0 level at fx - dBm0 level at 1kHz where 300Hz < fx < 3.400kHz
R
X
Z[1..3] = 0 B[1..8] = 0 Reference frequency = 1kHz
Figure 14.
RECEIVE:
ATTENUATION (dB) 2 1.4 0.9 1 0.65 0.45 0.25 0 -0.25 -1 0 .3 .4 .6 1.0 2.0 2.4 3.0 3.4 3.6 FREQUENCY (KHz)
TRANSMIT:
ATTENUATION (dB) 2 1.4 0.9 1 0.65 0.45 0.25 0 -0.25 -1 0 .2 .3.4 .6 1.0
D96TL257A
2.0
2.4
3.0 3.4 3.6 FREQUENCY (KHz)
37/49
STLC3040
GAIN TRACKING Rx/Tx
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = 00 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 50 GR = FFh GX = FFh K = 1000h | 1000h | 0h | 0h | 0h | 1000h | 0h | 0h | 0h (4096) | (0) | (0) | (0) | (4096) | (0) | (0) | (0) | CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = 03 (255) (255) (4096)
Voutref = voltage on Vout with DDref = -10dBm0 Voutmes = voltage on Vout with -55dBm0 < DDmes < 3dBm0 Rx gain tracking = 20 log (Vout mes / Voutref) - (DDmes - DDref) Tx gain tracking = starting from the same consideration of the absolute gain.
target DU represents the dBm0 level expected on DU with a certain set of coefficient and a Vrac of 41.4Vrms VRac_ref is the amplitude of the sine wave (1kHz) to be applied on RAC (pin 16) in order to expect on DU a Vpcm dBm0 level with the same set of coefficient. target DU (dBm0) = 3.14 + 20 ((0.0414 3 (2 sqr(2)) / 1.514) 16 (K/8192) (X[1]/8192) (GX/256) 0.966) VRac_ref = 41.4mV 10^ ((Vpcm - target DU)/20)
R
X
B[1..8] = 0 Z[1..3] = 0 Reference frequency = 1kHz Reference level on DD = -10dBm0 (or expected value at Vout, pin 26, in the range of 14.39mVrms) Figure 15. (Valid for 0 < Tamb < 70C)
RECEIVE:
G (dB) 2 1.4 1 0.5 0.25 0 -0.25 -0.5 -1 -1.4 -2 -70 -60 -55 -50
D96TL258A
DUref = dBm0 level at DU with (target DU) ref = 10dBm0 DUmes = dBm0 level at DU with -55dBm0 < (target DU) mes < 3dBm0 Tx gain tracking = (DUmes - DUref) - ((target DU)mes - (target DU)ref)
-40
-30 -20 -10 INPUT LEVEL (dBm0)
0
3
10
TRANSMIT:
G (dB) 2 1.4 1 0.5 0.25 0 -0.25 -0.5 -1 -1.4 -2 -70 -60 -55 -50
D96TL262
-40
-30 -20 -10 INPUT LEVEL (dBm0)
0
3
10
38/49
STLC3040
SIGNAL TO NOISE RATIO Use the same Test Configuration of Gain Tracking Test. Figure 16. (Valid for 0 < Tamb < 70C)
S/D (dB) 35 30 25 20
Input Level (dBm0) -44.5 -40 -30 -20
S/DCLOSED LOOP (dB) 19.725 24.625 32.716 34.709 34.97 34.997 35
TRANSMIT:
15
-10
10 5 0 -50 S/D (dB) 35 30 -45 -40 -35 -30 -25 -20 -15 -10 -5 INPUT LEVEL (dBm0) 0 5
0 +3
Input Level (dBm0) -44.5 -40 -30 -20
S/DCLOSED LOOP (dB) 23.02 27.9 34.538 34.95 35 35 35
RECEIVE:
25 20 15 10 5 0 -50 -45 -40 -35 -30 -25 -20
D96TL259C
-10 0 +3
-15 -10 -5 0 INPUT LEVEL (dBm0) 5
CLOSED LOOP as per Q.552 ITU-T specifications with line impedance = 900
Figure 17: Overload Compression (Transmit: measured with sine wave f = 984Hz).
9 8
OUTPUT POWER (dBm)
7 6 5 4 3 2 1 0 1 2 3 4 5 INPUT POWER (dBm) 6 7 8 9
D96TL266A
ACCEPTABLE REGION
39/49
STLC3040
IDLE_CHANNEL NOISE Rx/Tx (TTX off) (Test Cond. 1)
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = 05 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 50 GR = FFh GX = B4h K = 05A0h | 09CDh | 042Dh | 0919h | 39BBh | 178Dh | 0E31h | 2922h | 0CCFh | 39D3h | 0859h | 21EDh | 000Dh | 3F0Eh | 00AB | 039Eh | 0483h | 044Fh | 03AB | 3C00h CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = FF (255) (180) (1440) (2509) | (1069) | (2329) | (-1605)| (6029) | (3633) | (-5854) | (3279) | (-1581) | (2137) | (-7699) | (13) | (-242) | (171) | (926) | (1155) | (1103) | (939) | (-1024) |
DD = idle code (A_law) Id_ch_noise at Tx = dBm0 level at DU Id_ch_noise at Rx = voltage (rms) at Vout (Vrms) (psophometric weighted)
R
X
Z
B
OUT OF BAND NOISE (Test Cond. 2)
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = A5 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 50 GR = FFh GX = FFh K = 05A0h | 1000h | 0h | 0h | 0h | 1000h | 0h | 0h | 0h | 39D3h | 0859h | 21EDh (4096) | (0) | (0) | (0) | (4096) | (0) | (0) | (0) | (-1581) | (2137) | (-7699) | CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = FF (255) (255) (1440) Out of band signal at Analog output (Rx)
DD 5 frequencies between 2.8 and 3.8kHz + single frequency at 1kHz, the total amplitude is 0dBm0 (in this condition the expected value on 2W at 1kHz is about 23mVrms) OBN on Vout = Vout @ (32KHz 5freq.) Vout @ 1kHz
R
OBN (out of band noise) min 31dB
Out of band signal at Digital output (Tx)
X
Z
B[1..8] = 0 Z[1..3] = 0
40/49
VRAC = 5 frequencies between 32kHz - 3.8kHz and 32kHz - 2.8kHz + single frequency at 1kHz. The total amplitude to be applied on VRAC (pin 16) is calculated applying the same law of the absolute gain. VRACpicco = 133mV. OBN on Tx = dBm0 level at 1kHz - dBm0 level at each frequency reflected in band. OBN (out of band noise) min 25dB.
STLC3040
ECHO CANCELLING (Test Cond. 3)
CR[ 1] = 20 *) CR[ 2] = 00 CR[ 3] = A5 CR[ 4] = FD CR[ 5] = 60 CR[ 6] = 50 GR = FFh GX = FFh K = 0100h | 1FFFh | 0h | 0h | 0h | 1FFFh | 0h | 0h | 0h | 0800h | 3000h | 1000h | 3FE0h | 0h | 14h | 34h | 22Ch | 4h | 8h | 3FE0h (8191) | (0) | (0) | (0) | (8191) | (0) | (0) | (0) | (2048) | (-4096) | (4096) | (-32) (0) (20) (52) (556) (4) (8) (-32) | | | | | | | | CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = FF (255) (255) (256)
DD = tone at 1kHz and -5dBm0 measured_result = (tone level on DD) - (tone level onDU)
R
X
Z
B
*) CR[1] = 20h means digital loop-back 2 on.
RETURN LOSS (Test Cond. 4)
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = A5 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 60 GR = 0 GX = 0 K = 05A0 (1440) R[1..4] = 0 X[1..4] = 0 Z | 39D3h | 0859h | 1E13h (-1581) | (2137) | (7699) | CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = FF
multitone applied on RAC of amplitude 100mVp and measure performed on Vout
COFISLIC return loss F(s) - F(m) ---------------F(s) + F(m)
where F(s) is the ideal transfer function (RAC/Vout) from simulation F(m) is the measured transfer function
B[1..8] = 0
41/49
STLC3040
P.S.R.R. from VEE and VCC (Test Cond. 5)
CR[ 1] = 00 CR[ 2] = 00 CR[ 3] = A5 CR[ 4] = F9 CR[ 5] = 60 CR[ 6] = 50 GR = FFh GX = B4h K = 05A0h | 09CDh | 042Dh | 0919h | 39BBh | 178Dh | 0E31h | 2922h | 0CCFh | 39D3h | 0859h | 21EDh | Dh | 3F0Eh | 00ABh | 039Eh | 0483h | 044Fh | 03ABh | 3C00h CR[ 7] = 1C CR[ 8] = 08 CR[ 9] = 2F CR[10] = 00 CR[11] = 10 CR[12] = FF (255) (180) (1440) (2509) | (1069) | (2329) | (-1605)| (6029) | (3633) | (-5854) | (3279) | (-1581) | (2137) | (-7699) | (13) | (-242) | (171) | (926) | (1155) | (1103) | (939) | (-1024) |
R
X
DD = idle code Stimulus applied on VEE and VCC separately as a multitone (5 tone) of amplitude 100mVp PSRR on Rx (Vout) = 20 log (Vout at each tone / amplitude of the same tone applied on VEE or VCC) if referred to TIP/RING wire = above measure - 20log(20) (20 is due to the effect of closed loop) PSRR on Tx (DU) considering as dBm0 reference level an amplitude of 0.775Vrms = 20 log ((0.775 10^ (dBm0 level at each tone / 20)) / amplitude of the same tone applied on VEE or VCC)
Z
B
RING FUNCTIONALITY (Test Cond. 6)
f ring = 50Hz 2 WRNG = as volt on = CR9 [6..4] = ((CR9 [3..0] 2.039 Vrms + 34.4 Vrms)/40)/ 2 1 + (fring 200Hz) Ring ON
IHOOK_RING = {(1+CR5 [7..4]) 9.6mA/16}/50 RVR if 1 Vring on TIP/RING = Vring 17/13 CR[ 7] = 1C CR[ 1] = 80 CR[ 8] = 08 CR[ 2] = 03 CR[ 9] = Ring f/V CR[ 3] = 20 CR[10] = FF CR[ 4] = F9 CR[11] = 10 CR[ 5] = I prog CR[12] = FF CR[ 6] = FC
2WRNG (reported on TIP/RING wire) = (Vout pk 40) / sqr (2)
Ring PAUSE
2WRNG = V2wpk
GR = GX = 40h (64) K = 06A1h (1697) Z = [1..3] = 0 B = [1..8] = 0
R | 1000h | 0h | 0h | 0h | 1000h | 0h | 0h | 0h (4096) | (0) | (0) | (0) | (4096) | (0) | (0) | (0) |
X
42/49
STLC3040
TELETAX (Test Cond. 7) 2WTTX amplitude on Vout = (10Vrms (CR10[7..0] / 255))/40 TTx offset = CR10 [7..3] 15mV + X where X depends on normal or boosted battery
CR[ 1] = 01h CR[ 2] = 00h CR[ 3] = A5h CR[ 4] = F9h CR[ 5] = 60h CR[ 6] = 50h GR = FFh GX = B4h K = 05A0h | 09CDh | 042Dh | 0919h | 39BBh | 178Dh | 0E31h | 2922h | 0CCFh CR[ 7] = 1Ch CR[ 8] = 10h CR[ 9] = 2Fh CR[10] = 32h CR[11] = 10h CR[12] = FFh (255) (180) (1440) (2509) | (1069) | (2329) | (-1605)| (6029) | (3633) | (-5854) | (3279) | Z | 39D3h | 0859h | 21EDh | 000Dh | 3F0Eh | 00AB | 039Eh | 0483h | 044Fh | 03AB | 3C00h (-1581) | (2137) | (-7699) | (13) | (-242) | (171) | (926) | (1155) | (1103) | (939) | (-1024) |
B
R
TTx amplitude on TIP/RING wire = Vout TTX 40 TTx Offset = Vout dc level measurement of 2nd/3rd harmonic noise (psoph. weighted on Vout)
X
HALF BATTERY DETECTION (Test Cond. 8)
CR[ 1] = 00h CR[ 2] = 03h CR[ 3] = 00h CR[ 4] = F9h CR[ 5] = 60h CR[ 6] = FEh GR = 40h GX = 40h K = 06A1h CR[ 7] = FCh CR[ 8] = 08h CR[ 9] = 2Fh CR[10] = 00h CR[11] = 10h CR[12] = DFh (64) (64) (1697)
target VBIM (VBIMT) represents the voltage to supply the VBIM (Pin 25) to toggle the SR.5 bit (VB_2) target VBIM =
(CR8 [7.5] + 1) 125 drop =2 + IT RDC 0.288 + IT RDC RDC 2
Where: IT = -440A drop = VOUT for IT = 0 RDC = 820
Z = [1..3] = 0h (0) B = [1..8] = 0h (0)
R | 1000h | 0h | 0h | 0h | 1000h | 0h | 0h | 0h (4096) | (0) | (0) | (0) | (4096) | (0) | (0) | (0) |
If STLC3040 is in kit with HV (L3000N, L3000S, STLC3170) the SR.5 bit (VB_2) toggles when |VLINE| > |VOL / 2| see 4.7.1.1 paragraph.
Figure 18.
X
chip status: conversation normal polarity
DU 6 26 VOUT
IT
19
25
VBIM
440F
D98TL379
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STLC3040
GROUP DELAY Guaranteed by design Group Delay absolute values: Signal level 0dBm0
Symbol DXA DRA Parameter Transmit delay Receive delay Test condition f = 1.5kHz f = 1.5kHz Min. Typ. Max. 300 250 Unit s s
Figure 19: Group Delay Distortion receive and transmit: Signal level 0dBm0, fTEST @ TGmin
500
400
TG( s)
300
200 150 100 85 0 0.5
0.6
1
1.5
2 2.5 FREQUENCY(KHz)
2.6
2.8
3
3.5
D97TL299
4
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STLC3040
Table 13: Complete list of mode control bits.
Mode name for SLIC Kit Ext. Ind. Stand-by Ground Start Loop open Conv. N.P. Conv. R.P. Boost N.P. Boost R.P. Conv. NP+ TTx 12kHz/16kHz Conv. NP+ TTx Reversal Conv. RP+ TTx 12kHz/16kHz Conv. RP+ TTx Reversal Boost NP + TTx 12kHz/16kHz Boost NP + TTx Reversal Boost RP + TTx 12kHz/16kHz Boost RP + TTx Reversal Ring. Pause red. Power Ring red Pow Ring red Pow + Reversal Stand-By Ring Pause Ring Pause + Reversal Ringing Ringing + RP CI.7 CI.6 CI.5 CR1.7 CR8.3 CR0.5 CR1.6 CR7.1 C/I | Hook CR1.3|CR1.2 | X |X 0|0 0|0 0|0 1|1 X|X 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 0 | 0 or 1 | 1 1|0 1|0 1|0 1|0 1|0 1|0 0|1 0|1 0|1 0|1 0|1 0|1 X X X X X X X X X X 0 1 0 1 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 0 0 1 1 0 0 1 1 X X X 0 1 X X 0 1 0 0 1 1 X X X X X X X X X X X X X X X X X X 0 0 1 1 0 0 0 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X 1 0 0 X X X X X X X X X X X X X X 1 0 0 X X 1 0 X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X 0 1 0 0 1 1 X X 0 1 0 1 X X X X X X X X X X X X Mode LV Part Poweden StdBy StdBy StdBy StdBy Act. Act. Act. Act. Act. + OF Act. Mode HV Part PoweDen + 2 15k StdBy StdBy Acts. HiA Act. Act. + RP Boost 6V Interface PDN C1 C2 Hiz not Vlv Vlv LoZ Vhv Vhv LoZ Vhv Vhv LoZ Vhv Vmv LoZ Vmv Vhv HiZ LoZ Vlv Vlv LoZ Vhv Vmv Vhv Vlv LoZ Vmv Vmv
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 0 1 0 0 1 1
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 X 0 0 1 1 1 X
0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 1 1 1 0 0 0 1 0 1 0 0 0 1 0 1
0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X 1 X X X X X 1 X X X X X
PowDen PowDen
Boost+RP LoZ Vmv Vlv Act. Act. + RP LoZ Vhv Vmv LoZ LoZ Vhv Vlv Vhv Vlv
Act. + OF Act. + RP Act. Act. + OF Act. Act. + OF Act. StdBy StdBy StdBy Ring +RB Ring +RB StdBy StdBy Ring Ring Ring +RB Ring Act. Boost Boost + RP Boost + RP Boost StdBy StdBy Act. Ring Ring +RP StdBy Act. Ring Ring +RP Ring Ring
LoZ Vhv Vmv LoZ Vmv Vmv LoZ Vmv Vlv LoZ Vmv Vlv LoZ Vmv Vmv LoZ Vhv Vhv LoZ Vhv Vhv LoZ Vhv Vmv LoZ Vlv Vmv LoZ Vlv Vlv
LoZ Vhv Vhv LoZ Vhv Vmv LoZ Vlv Vmv LoZ Vlv Vlv
LoZ Vlv Vmv LoZ Vlv Vmv LoZ Vlv LoZ Vlv LoZ LoZ LoZ LoZ LoZ LoZ LoZ LoZ LoZ LoZ LoZ LoZ Vmv Vmv Vmv Vmv Vmv Vmv Vlv Vlv Vlv Vlv Vlv Vlv Vlv Vlv Vhv Vhv Vhv Vhv Vhv Vhv Vhv Vhv Vhv Vhv Vhv Vhv
Ring +RB Ring +RP Ring Ring +RP StdBy StdBy Act. Act. +OF Ring Ring +RB StdBy StdBy Act. Act. +OF Ring Ring +RB HiA HiA HiA HiA HiA HiA HiB HiB HiB HiB HiB HiB
HiA
HiB
'0 | 1': at the Bits HiA and HiB means HiA = 0 and HiB = 1. 'X': don't care means any combination is valid in this mode. 'LoZ': The PDN output (LW Part) pin has low impedance to ground.
'+RB': Additional ring burst on. '+RP': Additional DC voltage in A/B wire reversed. 'HiZ': The PDN output Pin (LV partI has high impedance or +5V to ground).
'+OF': Additional out of band frequency. '+BB': Feeding with additional +Vbatt.
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STLC3040
TIMING OF GCI INTERFACE Figure 20: DCL, FSC, DU and DD Characteristics.
tDCL
tDCLh
DCL
tFSC_H tFSC_S tFSC
FSC
tDD_H tDD_S
DD
tdDU
DU
D96TL268
Switching characteristics
Symbol tDCL tDCL tFSC tFSC S tFSC H tDD S tDD H tdDU Parameter Period DCL 'slow' mode (*) Period DCL 'fast' mode (**) DCL Duty Cycle Period FSC FSC set-up time FSC hold time DD data in set-up time DD data in hold time DU data out delay 40 70 40 20 50 150 (***) 250 125 tDCLh min. Limit Values typ. 1/2048kHz 1/4096kHz 60 % s ns ns ns ns ns max. Units
(*) DCL = 2048KHz: tFSC = 256 * tDCL (**) DCL = 4096KHz: tFSC = 512 * tDCL (***) Depending on Pull up resistor (typical 1....10k)
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STLC3040
APPENDIX 1 Internal Protections of digital pins. Figure A1.
INPUT VPOS
PAD
VNEG OUTPUT VPOS
VNEG
VNEG
D97TL300
VPOS = VCC or VDD VNEG = DGND or AGND or VEE
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STLC3040
mm MIN. A B C D d1 d2 E e e3 F F1 G M M1 1.16 1.14 14.99 1.27 12.7 0.46 0.71 0.101 0.046 0.045 17.4 16.51 3.65 4.2 2.59 0.68 16 0.590 0.050 0.500 0.018 0.028 0.004 TYP. MAX. 17.65 16.65 3.7 4.57 2.74 MIN. 0.685 0.650 0.144 0.165 0.102 0.027 0.630 inch TYP. MAX. 0.695 0.656 0.146 0.180 0.108
DIM.
OUTLINE AND MECHANICAL DATA
PLCC44
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STLC3040
ESD - The STMicroelectronics Internal Quality Standards set a target of 2 KV that each pin of the device should withstand in a series of tests based on the Human Body Model (MIL-STD 883 Method 3015): with C = 100pF; R = 1500 and performing 3 pulses for each pin versus VCC and GND. Device characterization showed that, in front of the STMicroelectronics Internaly Quality Standards, all pins, of STLC3040 except H.V ones (11, 12), withstand at least 1.5kV. H.V. pins n. 11, 12 withstand up to 350V due to their specific functionality. The above points are not expected to represent a pratical limit for the correct device utilization nor for its reliability in the field. Nonetheless they must be mentioned in connection with the applicability of the different SURE 6 requirements to STLC3040. Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com
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